Systems and methods for obfuscating a circuit design

ABSTRACT

Systems and methods for obfuscating a circuit design are described. One of the methods includes receiving the circuit design from a user computing device. The circuit design includes a plurality of circuit components. The method further includes obfuscating each of the circuit components by transforming layout features associated with the circuit design into a generic layout feature representation. The generic layout feature representation excludes scaled representations of the layout features. The method also includes generating a visual representation of the obfuscated designs. Each of the obfuscated designs has an input port and an output port. The method further includes enabling placement of the obfuscated designs and routing between the input ports and the output ports of the obfuscated designs. The method includes generating an obfuscated integrated circuit design having a master input port, a master output port, the obfuscated designs, and the routing between the obfuscated designs.

CLAIM OF PRIORITY

The present patent application is a continuation of and claims thebenefit, under 35 U.S.C. § 120, of U.S. nonprovisional application Ser.No. 15/633,412, filed on Jun. 26, 2017, and titled “Systems and Methodsfor Obfuscating a Circuit Design” which claims priority, under 35 U.S.C.§ 119(e), to a U.S. provisional patent application having applicationNo. 62/359,858, filed on Jul. 8, 2016, and titled “Systems and Methodsfor Engineering Integrated Circuit Design and Development”, both ofwhich are incorporated by reference herein in their entirety.

FIELD

The present embodiments relate to systems and methods for engineeringcircuit design and development, and cloud systems that enable designersto access design tools used for a design of integrated circuits, methodsfor verifying designs, methods for posting designs to an online designengineering system, systems and methods for obfuscating a circuitdesign, and methods for generating integrated circuits manufacturingmodels to interface with fabrication entities. Some embodiments enabledesigners to generate prototype integrated circuits and validatespecifications for the integrated circuits, and the prototype integratedcircuits and the specifications are then made available for use inapplication specific integrated circuits (ASICs), systems on a chip(SOC), and/or for use in other electronic systems, circuits, products ordevices.

BACKGROUND

Integrated circuits (ICs) include electronic components built into anelectrical connection network on a semiconductor substrate. IC design isusually divided into categories of digital and analog IC design. DigitalIC design is used to produce digital electrical circuit components suchas microprocessors, field programmable gate arrays (FPGAs), and memorydevices. Digital design sometimes focuses on logical correctness,maximizing circuit density, and placing circuits so that clock andtiming signals are routed efficiently. Analog IC design representsphysical conditions, such as pressure or temperature, or othercontinuous functions in electronic circuitry, and has manyspecializations including power IC design, sensor interface IC designand radio frequency (RF) IC design. In some instances, ICs can bedesigned to include both analog and digital components. A design relieson engineering specifications that are tuned to achieve a specificfunction, device or application.

However, it is difficult to generate a design of an IC and to fabricatea prototype of the IC. It is in this context that embodiments describedin the present disclosure arise.

SUMMARY

Integrated circuit design is typically conducted by design engineersthat have knowledge of electrical circuits and circuit functionality.However, to design integrated circuits, designers may not have access tospecialized software tools and to fabrication facilities. Once a designfor an integrated circuit (IC) is complete and validated by computermodeling using various software tools, the designer should validate thedesign by fabricating a prototype of the IC on a semiconductor wafer.The software tools generate manufacturing-aware electronic models thatshould be sent to the fabrication facilities. As noted, the designers donot have access to the fabrication facilities, which fabricates manylayers of the IC on a semiconductor wafer. Fabrication of asemiconductor wafer, as is generally known, is performed usingspecialized tools to perform operations such as, ion implant operations,photolithograph operations, etching operations, deposition operations,cleaning operations, and many more operations. Additionally, designersdo not have access to circuit libraries that are designed and/or used bythe fabrication facilities. The circuit libraries include specificationsfor layouts, connections and other rules so that the fabricationfacilities can fabricate the IC created by the designer, such as byusing cell layouts from a circuit library. Once the IC design isfabricated, the IC design is tested to validate its functionality.

As can be appreciated, designers do not have access to the process ofdesigning and validating ICs, do not have access to sophisticatedsoftware tools, do not have access to libraries of fabricationfacilities, and do not have access to financial capital to complete theIC design that can be used in a system or device. Designers that haveaccess to these resources are employed by companies that invest heavilyin maintaining the latest design tools and have either internalfabrication facilities or have established relationships with one ormore fabrication facilities. Although individual designers are able tocome up with unique and useful IC designs, they are not generally ableto generate IC designs and/or generate prototypes for validating theirIC designs outside of a company.

Embodiments of the disclosure provide apparatus, methods and computerprograms for developing IC designs, verifying functionality of ICdesigns before fabrication, generating a prototype of the IC resultingfrom the design, testing the IC in the form of a prototype, andvalidating the functionality against a specification. In one embodiment,the process of designing the IC, verifying the design of the IC, testingthe prototype of the IC, and generating validated specificationsutilizes an online design engineering system. The online designengineering system is implemented as a cloud-based infrastructure thatprovides designers with access to design software tools, access todesign libraries of fabrication facilities, and an infrastructure thatfacilitates verification and generation of prototypes of the IC from oneor more fabrication facilities. In one embodiment, the cloudinfrastructure of the online design engineering system enables designsto be shared with a community of designers or requesters, such ascustomers, that request a new design or a type of design similar to onealready designed by an engineering designer. In other embodiments, theonline design engineering system enables the customers or otherdesigners to post a request to the online design engineering system fora specific design, such as one having specific functional requirements.

Requesters that are interested in creating such a design will produce aspecification, which defines how the circuit design will function. Insome cases, more than one requester will submit a specification. In oneembodiment, the online design engineering system screens thespecifications to determine completeness and/or other metrics. Once aspecification is selected, a designer proceeds to create a circuitdesign, such as to create circuitry connections and to interconnectcells. This phase of the design includes producing a schematic, whichthen proceeds to physical layout description. The software toolsprovided by online design engineering system, in addition to enablingproduction of the schematic, and layout and design verification, enablean interface with the fabrication facilities for producing a prototype.In one embodiment, the online design engineering system providesdesigners with access to circuit libraries of a fabrication facility.The circuit libraries, by way of example, include cells that are used ina layout design and that include custom layout features. The customlayout features in the cells are regarded as confidential by thefabrication facility.

However, since the online design engineering system is providing accessto many individual designers, the online design engineering systemprovides access via an obfuscation layer. The obfuscation layer isconfigured to “black box” layout geometries and/or design rules of thecells, but still provides access to the cells, which include definedinputs and outputs. In one embodiment, the obfuscation layer is managedby the online design engineering system, so that many designers are ableto gain access to functional blocks of the cells associated with circuitlibraries, but the confidential information of the fabricationfacilities is not shared.

In a like manner, designers use the cells and other interconnections andother integration circuits, such as glue logic, to create theirproprietary circuit designs. Ways in which the designers interconnectthe cells, make specific connections, and/or routing is consideredconfidential to the designers. In one embodiment, a designer levelobfuscation layer is provided, so that circuit designs shared with thecommunity and/or used by entities wishing to implement the proprietarycircuit design in their IC are not provided with such details.

In an embodiment, a designer provides a circuit design with aspecification that he or she believes meets a functional requirement foran IC, such as an IC that is requested by an entity or another member,such as a requester, of the online design engineering system. In somecases, multiple designers produce their own circuit designs andassociated specifications. In an embodiment, the online designengineering system screens the designs for completeness, compliance tospecifications, and manufacturability.

In one embodiment, a circuit design is connected to an integrationcircuit design, such as a glue logic design, that is provided by theonline design engineering system to generate an integrated circuit chipdesign. Moreover, another circuit design is connected to the integrationcircuit design, such as the glue logic design, to generate anotherintegrated circuit design. A designer of the circuit designs is able touse the online design engineering system to generate manufacturing-awareelectronic models that are sent to the fabrication facilities togenerate prototypes. Both the integrated circuit designs are fabricatedon a shuttle, such as a wafer, to generate prototypes of integratedcircuit chips. The prototypes are coupled to a printed circuit boardthat is provided by the online design engineering system, and theprinted circuit board is coupled to a computer having software fortesting the prototypes. The software is provided by the online designengineering system. The designer is able to use the online designengineering system to test the prototypes.

In an embodiment, the online design engineering system, whichfacilitates a crowd-sourcing platform, is provided for semiconductorintellectual property blocks (IP) and ICs. The online design engineeringsystem is provided to address market access, and development cost andcollaboration barriers that inhibit innovation in hardware productdevelopment.

Using the online design engineering system, the community members createIP and ICs and sell the IP and ICs to potential requesters, such as,system developers and device developers, around the world. Using theonline design engineering system, the requesters request the communityto design a chip or collaborate on interesting projects. In anembodiment, the online design engineering system allows the members,such as designers, of the community to design at no upfront cost. Theonline design engineering system manages an interface to foundry processtechnology so that the community members cost-effectively convert ideasinto prototypes without significant administrative overhead. The onlinedesign engineering system provides a weighted revenue sharing processbased on community members' contributions.

Several features of the online design engineering system include:

-   -   Providing a cloud based system for access by the members. For        example, the customers access the online design engineering        system via their corresponding web accounts, e.g., user        accounts, etc., and post projects for which they desire to have        IC design guidance or execution. Moreover, the designers post        circuit designs of IP or integrated circuit chip designs of ICs        into the online design engineering system for the customers to        license. The customers and the designers, in an embodiment, set        their own terms of payment, e.g., amount of payment, upfront        payment, royalty amount, royalty percentage, etc.    -   Providing a design environment. For example, a registered        community member accesses the design tools for free, such as        without cost, to the registered community member. In an        embodiment, electronic design automation (EDA) tools are        provided via the online design engineering system to the        designers. Also, in one embodiment, additional capabilities to        integrate the design tools into a logical flow are provided by        the online design engineering system.    -   Providing a foundry interface. The online design engineering        system provides the designers access to foundry process        technology and cell libraries. The online design engineering        system provides the ability to generate manufacturing-aware        electronic models that are sent to the fabrication facilities to        generate prototypes. This eliminates a major barrier for the        designers to generate designs of IPs or ICs, and fabricate        prototypes from the designs.    -   Providing ratings, badges and reviews. For example, the online        design engineering system facilitates review and rating of        designs of IPs or ICs or of the prototypes of the designs. In an        embodiment, the badges are awarded for particular areas of        capability.    -   Providing a community-oriented design process. For example, the        online design engineering system facilitates an IC or IP        development process regardless of a specific application, such        as, definition, schematic capture, simulation, layout, place and        route, and characterization. As such, the development process is        divided into various discrete steps and automated with different        participants at each stage. In an embodiment, competitions are        held to address each stage along the development process. The        online design engineering system leverages the community of        designers who compete by submitting potential solutions to each        step in the development process.    -   Providing multiple winners. For example, to obtain multiple        entries, multiple winners, such as the designers, are selected        at each of various stages of the development process with        payments of various amounts to each of the winners. In an        embodiment, all entries, such as designs, win or lose, are        placed in the online design engineering system for subsequent        demand.    -   Providing datasheet driven community design. For example, the        development process begins with creation of an on-line data        sheet that is specific to a class of product or application. The        data sheet is a central form of communication throughout a        design generation, design verification, prototype validation,        and sign-off process. The data sheet is transformed from being a        descriptive document produced after a design is completed and        used for sales purposes into a design control document.    -   Providing an iterative community design. For example, the        development process is an inherently iterative process that        reduces time and costs associated with: (i) unintended or        unforeseen results within a given stage in the development        process, such as yield or performance results from core/cell        integration and design/process interaction within chip        development; (ii) unforeseen interactions and tradeoffs between        or among the stages, such as, relative benefits or issues        between software and hardware components within a system;        and (iii) unforeseen problems in moving a product from design to        manufacture. The online design engineering system is architected        to leverage the community to expedite achievement of the        unintended or unforeseen results, the unforeseen interactions        and tradeoffs, and the unforeseen problems with lower costs than        that associated with a conventional process of fabricating an        integrated circuit.    -   Provides a multi-threaded community design. For example,        hardware and IC research and development is experimental and        often uses trial and error to get to an optimal outcome,        particularly for IoT and other emerging hardware. The design        engineering facilitates generation of alternative paths that are        invoked at various times in a research and development process        in ways that are not foreseen at the beginning of the        development process. The online design engineering system        overcomes resource limitations in internal development teams and        time-consuming nature of qualifying third party outsourced        developers, reduces chances of cost overruns, reduces        occurrences of time to market problems, and reduces chances of        providing sub-optimal solutions. In an embodiment, the online        design engineering system is architected to allow for dynamic        multi-threading to introduce multiple potential solutions to a        research and development process with little if any additional        cost or time to market.    -   Providing community verification and validation. For example,        the online design engineering system provides pre-silicon        verification of designs, and post silicon validation of the IP        or IC. To illustrate, the online design engineering system        provides breadth and accuracy of the verification and validation        by providing simulation tools for running simulations on the        designs. Moreover, the designers of the community and a design        engineering entity expand both the breadth and accuracy of        verification by replicating results, independently. To further        illustrate, simulation tools are applied by a designer to        generate results of a simulation and the same or different        simulation tools are applied by another designer or the design        engineering entity to generate results of another simulation.        The results of both simulations act as a check against each        other or a verification on top of another. In one embodiment,        different simulation tools are used by the design engineering        entity or an independent community member, such as a user, than        that used by the designer. For example, the simulation tools        applied by the design engineering entity or the independent        community member not only include simulation tools used by the        designer but also include additional simulation tools. As an        example of the validation, the design engineering entity offers        the community with an integrated circuit test chip and related        software for community validation of a circuit design. Results        of the verification and the validation are made transparent to        the community to verify and validate the results.    -   Providing market perceived quality. For example, a perceived        quality of results of the verification or validation is improved        when the design engineering entity re-verifies results of the        verification or validation and when any community member        re-verifies results of a simulation, e.g., performed by another        designer, etc., or validates parameters of a chip. In an        embodiment, a use counter tool of the online design engineering        system counts usage, such as, a number of times a design is        implemented within an integrated circuit, a number of times the        design is commented on positively by designers, and/or a number        of times a simulation is run on the design for which the design        passes a simulation, of a design and generates reviews and        ratings for the usage and reports the reviews and ratings in the        online design engineering system, further improving market        confidence and perception. For example, perception increases        exponentially with a reported number of uses and re-simulations.    -   Providing try before buy technology. A cost benefit of the        online design engineering system is improved by the try before        buy technology, provided by a crowd-sourcing platform of the        online design engineering system. The designers use the design        tools and one or more IP libraries for no upfront payment or a        minor upfront payment to the online design engineering system,        and deploy in prototypes of one or more designs for an        additional affordable fee. This allows for multiple development        paths and therefore higher probability of success of the        customers and the designers, at a very lower cost through        prototype, than that possible by conventional approaches.    -   Providing foundry technology obfuscation. In an embodiment, the        designers access foundry processes, e.g., IP libraries of        foundry entities, etc., used to generate a circuit design. The        foundry entities typically work on a peer-to-peer basis through        an NDA with the designers to protect their underlying        technology. This is particularly sensitive in analog design        where the designers interact at an intimate level with an        underlying process technology. The online design engineering        system inserts an obfuscation functionality in a design flow to        obfuscate critical underlying foundry process technology, e.g.,        Graphics Database System (GDS) layers obtained from a library of        GDS layers, etc. In one embodiment, the online design        engineering system provides an approach to simulation and other        design steps where process data is maintained in a protected        location and accessed by tools without visibility to the        designer. For example, while running a simulation, the online        design engineering system does not allow access to data that is        output at an intermediate node in a layout design or to GDS        layers of the layout design. The GDS layers is proprietary to        the design engineering entity. This feature of the online design        engineering system eliminates the need for a foundry        non-disclosure agreement (NDA).    -   Providing designer technology obfuscation: A feature of        crowd-sourced marketing and sale of a design is that the        customers work with the design at an intimate level but that        critical technology and design features of the design are not        exposed. This is done without specific NDA between the requester        and the designer. The approach here is analogous to the foundry        technology obfuscation above, except that obfuscated information        is the design. For example, a schematic of the circuit design        generated by a designer cannot be accessed by another designer        or a requester without permission from the designer.    -   Providing a collaborative interactive specification. For        example, the customer posts a desired specification within a        data sheet for an integration circuit and the community        interacts with the data sheet to define a deliverable        specification. This approach leverages a capability and size of        the community to achieve an optimal outcome for the customer,        regardless of knowledge of the customer regarding IC or IP        design.

In one embodiment, a method for providing an online design engineeringsystem to fabricate a prototype of a circuit is described. The methodincludes providing, by a management server, access to a designengineering system (DES) access application for accessing a data sheet.The method includes receiving, by the management server, a specificationof a design of the circuit via the data sheet. The method includesproviding, by the management server, access to the data sheet to aplurality of user computing devices operated by users of the community.The method further includes providing access to a circuit design toolvia a plurality of user accounts of the users for facilitatinggeneration of a plurality of circuit designs. The method includesreceiving, by the management server, the circuit designs of the circuitvia the plurality of user accounts. The method further includes anoperation of analyzing, by an automatic certification server, thecircuit designs to determine whether the circuit designs pass anautomatic circuit design test. The method includes selecting, by themanagement server, two of the user accounts of two of the users forwhich two of the circuit designs pass the automatic circuit design test.The method includes an operation of providing, by the management server,access to a layout design tool to the two user accounts for generatingtwo layout designs of the circuit. The method includes receiving, by themanagement server, the two layout designs via the two user accounts ofthe community. The method also includes an operation of analyzing, bythe automatic certification server, the two layout designs to determinewhether the two layout designs pass an automatic layout design test. Themethod includes selecting, by the management server, one of the two useraccounts for which one of the two layout designs of the circuit passesthe automatic layout design test. The method includes generating, by themanagement server, a file, such as a Graphics Database System II (GDSII)file, including the layout design of the circuit upon selecting the useraccount for which the layout design passes the automatic layout designtest. The method includes sending, by the management server, the file toan integrated circuit fabrication facility to fabricate a prototype ofthe circuit based on the layout design.

In an embodiment, the method further includes obfuscating portions ofthe circuit designs before providing access to the circuit designs toadditional users of the community via corresponding additional useraccounts. The method includes obfuscating portions of the layout designsbefore providing access to the layout designs to the additional usersvia the corresponding additional user accounts.

In an embodiment, a method for obfuscating a circuit design isdescribed. The method includes receiving the circuit design from a usercomputing device via a computer network and a user account. The circuitdesign includes a plurality of circuit components and connectionsbetween the circuit components. The method further includes obfuscatingeach of the circuit components by transforming layout featuresassociated with the circuit design into a generic layout featurerepresentation. The generic layout feature representation excludesscaled representations of the layout features. The operation ofobfuscating is performed so that each circuit component is representedas an obfuscated design that has electrical characteristics of thecircuit component and excludes access to the layout features of thecircuit component. The method also includes generating a visualrepresentation of the obfuscated designs. Each of the obfuscated designshas an input port and an output port. The method further includesenabling placement of the obfuscated designs and routing between theinput ports and the output ports of the obfuscated designs. The methodincludes generating an obfuscated integrated circuit design having amaster input port, a master output port, the obfuscated designs, and therouting between the obfuscated designs. The obfuscated integratedcircuit design is accessible to simulate the circuit design withoutexposing the circuit design such that the simulation of the circuitdesign is performed while the circuit components are obfuscated.

In one embodiment, a system for obfuscating a circuit design isdescribed. The system includes a circuit design tool that receives thecircuit design from a user computing device via a computer network and auser account. The circuit design includes a plurality of circuitcomponents and connections between the circuit components. The systemfurther includes an obfuscator tool coupled to the circuit design tool.The obfuscator tool obfuscates each of the circuit components bytransforming layout features present in the circuit design into ageneric layout feature representation. The generic layout featurerepresentation excludes scaled representations of the layout features.The obfuscator tool performs the obfuscation to represent each circuitcomponent as an obfuscated design that has electrical characteristics ofthe circuit component and excludes access to the layout features of thecircuit component. The obfuscator tool generates a visual representationof the obfuscated designs. Each of the obfuscated designs has an inputport and an output port. The system includes a layout design toolcoupled to the circuit design tool and the obfuscator tool. The layoutdesign tool enables placement of the obfuscated designs and routingbetween the input ports and the output ports of the obfuscated designs.The obfuscator tool generates an obfuscated integrated circuit designhaving a master input port, a master output port, the obfuscateddesigns, and the routing between the obfuscated designs. The obfuscatedintegrated circuit design is accessible to simulate the circuit designwithout exposing the circuit design such that the simulation of thecircuit design is performed while the circuit components are obfuscated.

In an embodiment, a system for obfuscating a circuit design isdescribed. The system includes a circuit design tool that receives thecircuit design from a user computing device via a computer network and auser account. The circuit design includes a plurality of circuitcomponents and connections between the circuit components. One of thecircuit components is of a different type than one of remaining of thecircuit components. Each circuit component has an input and an output.The system further includes an obfuscator tool coupled to the circuitdesign tool. The obfuscator tool obfuscates the types of the circuitcomponents to generate an obfuscated design for each component. Thesystem also includes a layout design tool coupled to the obfuscatortool. The layout design tool receives, from the user computing devicevia the user account and the computer network, a request for accessingthe layout design tool. The obfuscator tool sends the obfuscated designof each of the circuit components to the user computing device via theuser account and the computer network when the request to access thelayout design tool is received.

Some advantages provided by the online design engineering systeminclude:

-   -   Enabling hardware, such as semiconductor chip, innovation by        lowering cost of fabricating a prototype. For example, in a        traditional semiconductor company, a cost of fabricating a        prototype is a fixed cost, e.g., people cost, salaries of        employees, etc. In the online design engineering system, people        costs are their opportunity cost, which are low. For example,        there are no salaries of the designers. Rather, each designer is        compensated in one of two ways, such as an award at the        completion of the design effort, or a percentage of the        generated revenue when their design is purchased through the        online design engineering. The online design engineering system        allows various designers to showcase their skills in generating        circuit designs to promote innovation at no or minimal cost to        the designers.    -   Lowering development cost of an integrated circuit chip.    -   Creativity of the community is far greater than creativity of        any one organization or person. The creativity of the community        is increased exponentially by connectivity, via user accounts,        etc., assigned to the members of the community.    -   Massive collaboration via the online design engineering system        between the users and the requesters.    -   Solving a problem of talent access limitation. Hardware        development has been a process of rapid evolution of a known and        finite set of platforms, such as personal computer (PC), phone,        and router, with known or predictable market sizes and needs.        Focus of such hardware development has been on high volume        standard IC products. However, Internet of Things (IoT)        development is different. IoT products are massively customized,        with unknowable potential. Semiconductor design of IoT products        employs the online design engineering system that supports mass        customization with significant trial and error. Traditional        semiconductor models are not conducive to this because of the        limited access to captive design talent. A crowdsourcing        development model provided by the online design engineering        system solves the problem of talent access limitation.

It should be appreciated that the present embodiments can be implementedin numerous ways, e.g., a process, an apparatus, a system, a piece ofhardware, or a method on a computer-readable medium. Several embodimentsare described below. Other aspects will become apparent from thefollowing detailed description, taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments are understood by reference to the following descriptiontaken in conjunction with the accompanying drawings.

FIG. 1A is a diagram of an embodiment of an online design engineeringsystem for illustrating a push operation.

FIG. 1B-1 is a diagram of an embodiment of an online design engineeringsystem to illustrate a pull operation.

FIG. 1B-2 is a diagram of an embodiment of a system to illustratecreations of designs of different electrical circuits based on a varietyof specifications.

FIG. 1C-1 is a diagram to illustrate processes for verification of adesign and acceptance of the design by a requester.

FIG. 1C-2 is a flowchart of an embodiment of a method for generating adesign and providing a requester access to the design.

FIG. 1D is a diagram to illustrate fabrication of prototypes of anintellectual property (IP) circuit, an integrated circuit (IC) or anInternet of things (IoT) circuit.

FIG. 1E is a diagram of an embodiment of the online design engineeringsystem for illustrating generation and verification of a design.

FIG. 1F is a diagram of an embodiment of the online design engineeringsystem to illustrate a fabrication of a prototype of a design.

FIG. 2 is a diagram of an embodiment of the online design engineeringsystem for illustrating communication with multiple user computingdevices and requester computing devices via a computer network.

FIG. 3 is a diagram of an embodiment of various tools of the onlinedesign engineering system.

FIG. 4A is a diagram of an embodiment of the online design engineeringsystem to illustrate obfuscation of a design and shuttling of multipleintegrated circuit chips on a wafer.

FIG. 4B-1 is a diagram of an embodiment of a schematic of a design and alayout of the design to illustrate obfuscation of the schematic and thelayout.

FIG. 4B-2 is a diagram of an embodiment of the online design engineeringsystem to illustrate shuttling of different integrated circuit chips ona wafer and testing of a prototype.

FIG. 5A is a diagram of an embodiment of the online design engineeringsystem to illustrate a competition for generating a design.

FIG. 5B is a diagram of an embodiment of a design challenge, which isposted within multiple user accounts when a requester via a requesteraccount posts a request for a design.

FIG. 6 is a diagram of an embodiment of a system to illustrate a serialprocess by which a design of an electrical circuit is generated.

FIG. 7 is a diagram of an embodiment of the online design engineeringsystem to illustrate a parallel process in which multiple prototypes ofmultiple designs are generated.

FIG. 8 is a diagram of an embodiment to illustrate fabrication andtesting of a prototype of an integrated circuit.

FIG. 9A is a diagram of an embodiment of an online design engineeringprocess executed by the online design engineering system to generate alayout design.

FIG. 9B is a block diagram of an embodiment of a design engineeringprocess for illustrating use of the online design engineering system infabricating an integrated circuit chip.

FIG. 9C is a block diagram of an embodiment of a design engineeringprocess for illustrating use of the online design engineering system infabricating an integrated circuit chip.

FIG. 10 is a diagram of an embodiment of a specification of a componentof the electrical circuit.

FIG. 11 is a diagram of an embodiment of the online design engineeringsystem that provides access to multiple users via the user accounts forgenerating a design and fabrication of an integrated circuit from thedesign.

FIG. 12 is a diagram of an embodiment of a system to illustrate aninterplay between a customer and a community to fabricate a prototype ofan integrated circuit chip.

FIG. 13A is a diagram of an embodiment of a design engineering methodthat is executed using the online design engineering system.

FIG. 13B is a diagram of an embodiment of a continuation of the designengineering method of FIG. 13A.

FIG. 13C is a diagram of an embodiment of a continuation of the designengineering method of FIG. 13B.

FIG. 14A is a diagram illustrating a flow of a design engineering methodthat is executed using the online design engineering system.

FIG. 14B is a diagram of an embodiment of a flow of a design engineeringprocess to illustrate an interaction of one of the users with a displayon a display device of a user computing device and to illustrate theonline design engineering system.

FIG. 15 is a diagram to illustrate a creation of a design.

FIG. 16 is a diagram of an embodiment of a design engineering method toillustrate a validation protocol and a validation protocol.

FIG. 17 is a diagram used to illustrate a relationship betweenconfidence of the community and requesters and fabrication entities, andto illustrate specification parameters coverage.

FIG. 18A-1 is a diagram to illustrate an embodiment of a designengineering method to illustrate a data sheet.

FIG. 18A-2 is a diagram to illustrate an embodiment of another portionof the design engineering method of FIG. 18A-1.

FIG. 18A-3 is a diagram to illustrate an embodiment of yet anotherportion of the design engineering method of FIG. 18A-1.

FIG. 18A-4 is a diagram to illustrate an embodiment of still anotherportion of the design engineering method of FIG. 18A-1.

FIG. 18A-5 is a diagram to illustrate an embodiment of another portionof the design engineering method of FIG. 18A-1.

FIG. 18B-1 is a diagram to illustrate an embodiment of a continuation ofthe design engineering method of FIG. 18A-5.

FIG. 18B-2 is a diagram to illustrate an embodiment of another portionof the design engineering method of FIG. 18B-1.

FIG. 18B-3 is a diagram to illustrate an embodiment of yet anotherportion of the design engineering method of FIG. 18B-1.

FIG. 18B-4 is a diagram to illustrate an embodiment of still anotherportion of the design engineering method of FIG. 18B-1.

FIG. 18C-1 is a diagram to illustrate an embodiment of a continuation ofthe design engineering method of FIG. 18B-4.

FIG. 18C-2 is a diagram to illustrate an embodiment of another portionof the design engineering method of FIG. 18C-1.

FIG. 18C-3 is a diagram to illustrate an embodiment of yet anotherportion of the design engineering method of FIG. 18C-1.

FIG. 18C-4 is a diagram to illustrate an embodiment of still anotherportion of the design engineering method of FIG. 18C-1.

FIG. 18C-5 is a diagram to illustrate an embodiment of yet anotherportion of the design engineering method of FIG. 18C-1.

FIG. 18C-6 is a diagram to illustrate an embodiment of still anotherportion of the design engineering method of FIG. 18C-1.

FIG. 19A is a diagram of a system to illustrate functionality of aworkspace application and storage of various files, such as a testbenchnetlist file and a specification file, within a searchable storage.

FIG. 19B is a diagram of an embodiment of the system of FIG. 19A toillustrate a storage of a circuit netlist file associated with aschematic in the searchable storage.

FIG. 19C is a diagram of an embodiment of the system of FIG. 19A toillustrate a simulation test performed on a design of a schematic.

FIG. 19D is a diagram of an embodiment of the system of FIG. 19A toillustrate storage of a results of the simulation test in a designdatabase.

FIG. 20A is a diagram of an embodiment of a portion of a data sheet.

FIG. 20B is a continuation of the data sheet of FIG. 20A.

FIG. 20C is a continuation of the data sheet of FIG. 20B.

FIG. 20D is a continuation of the data sheet of FIG. 20C.

FIG. 20E is a diagram of an embodiment of a portion of a data sheet.

FIG. 20F is a continuation of the data sheet of FIG. 20E.

FIG. 20G is a continuation of the data sheet of FIG. 20F.

FIG. 20H is a continuation of the data sheet of FIG. 20G.

FIG. 20I is a diagram of an embodiment of a portion of a data sheet.

FIG. 20J is a continuation of the data sheet of FIG. 20I.

FIG. 20K is a continuation of the data sheet of FIG. 20J.

FIG. 20L is a continuation of the data sheet of FIG. 20K.

FIG. 21 is a diagram to illustrate a variety of integrated circuit chipsthat are designed using the online design engineering system.

FIG. 22 is an embodiment of a computing device that is used to executethe design engineering methods described herein.

FIG. 23 is a diagram of an embodiment of a server to execute the designengineering methods described herein.

FIG. 24 is a diagram of an embodiment of a system to illustrate thatthere is no non-disclosure agreement (NDA) between fabrication entitiesand the community.

FIG. 25 is a diagram of an embodiment of a system to illustrate that auser uses a layout design of an integrated circuit chip with anotherlayout design of another integrated circuit chip to create yet anotherintegrated circuit chip design.

FIG. 26A is a diagram of an embodiment to illustrate generation ofobfuscated designs from a schematic.

FIG. 26B is a diagram of an embodiment of a workspace display toillustrate a manual placement of obfuscated designs and to illustratemanual generation of routes between the obfuscated designs.

FIG. 27 is a diagram of an embodiment of a system to illustrate anapplication of an obfuscator tool to a process design kit (PDK) that iscontrolled by a fabrication entity.

FIG. 28 is a diagram of an embodiment of a system to illustrate a trybefore buy option of the online design engineering system.

FIG. 29 is a diagram of an embodiment of an integrated circuit chipdesign that is obfuscated by the obfuscator tool.

FIG. 30 is a diagram of an embodiment of a system for mapping a GraphicsDatabase System (GDS) layer of a layout design to a plane.

FIG. 31 is a diagram of an embodiment of a system to illustrategeneration of a derived type from two or more GDS layers.

FIG. 32 is a diagram of an embodiment of a listing of obfuscator rulesthat are applied by the obfuscator tool to obfuscate one or more layoutfeatures of a layout design.

FIG. 33 is a diagram of an embodiment of an integrated circuit chipdesign, which is obfuscated by the obfuscator tool to generate derivedtypes.

FIG. 34 is a diagram of an embodiment of an integrated circuit chipdesign to illustrate multiple derived types.

FIG. 35 is a diagram to illustrate an embodiment of an obfuscatedintegrated circuit chip design that is generated from an unobfuscatedintegrated circuit chip design.

FIG. 36A is an embodiment of an unobfuscated layout design of aninverter.

FIG. 36B is a diagram of an embodiment of a top view of the layoutdesign of FIG. 36A.

DETAILED DESCRIPTION

The following embodiments describe systems and methods for engineeringcircuit design and development. It will be apparent that the presentembodiments may be practiced without some or all of these specificdetails. In other instances, well known process operations have not beendescribed in detail in order not to unnecessarily obscure the presentembodiments.

The online design engineering system connects circuit and systemdesigners with other circuit and system designers, customers orend-users and fabrication entities. The online design engineering systemallows various circuit designers to share various designs for zero ormarket-equivalent licensing fees or royalties. The designers, uponreceiving a request via the online design engineering system or withoutreceiving the request to generate one or more designs, submit thedesigns to the online design engineering system. In generatingschematics of the designs, the designers apply design tools that areprovided by the online design engineering system. Moreover, ingenerating physical layouts of the designs, the designers accessintellectual property (IP) libraries that are coupled to the onlinedesign engineering system. The designs are verified using one or moresimulation softwares provided by the online design engineering system.In one embodiment, a design engineering entity performs an independentverification of the designs by using the one or more simulationsoftwares and/or a different simulation software.

In an embodiment, one or more design level obfuscation layers areapplied by the online design engineering system to a schematic of acircuit design to hide connections between components of the circuitdesign, and/or the components of the circuit design, and/or the entirecircuit design. The design level obfuscation layers are applied toprotect intellectual property of a designer from being publiclyavailable via the online design engineering system.

In one embodiment, one or more obfuscation layers are applied to aphysical layout of a circuit design to hide connections between cells ofthe physical layout and/or to hide IP layers of the physical layout. Theobfuscation layers are applied by the online design engineering systemto protect intellectual property of a fabrication entity, such as afoundry, that provides an IP library from which the cells are accessedby a designer and to protect intellectual property of the designer. Inan embodiment, the fabrication entity is controlled by, such as undermanagement of or governed by, the design engineering entity. Forexample, all employees of the fabrication entity are employees of thedesign engineering entity. In one embodiment, the fabrication entity isindependent of control of the design engineering entity. For example,the fabrication entity is a separate organization from the designengineering entity and none of the employees of the fabrication entityand the design engineering entity are the same.

In an embodiment, an integrated circuit chip design is provided by theonline design engineering system. The integrated circuit chip designincludes a glue logic design or another integration circuit design thatis compatible with one or more designs that are generated by a designer.The one or more designs are coupled to the glue logic design or theother integration circuit design by the designer to create derivativesof the integrated circuit chip design and the derivatives are fabricatedon a shuttle to generate prototypes of integrated circuit chips. Thederivatives are verified using a validation software, such as aprototype tester and test report generator tool. Also, in an embodiment,the prototypes are tested using a printed circuit board and a computer.The computer is used to execute a test software of prototype tester andtest report generator tool. In an embodiment, the online designengineering system validates the prototypes independently of validationperformed by the designer. The independent verification increasesconfidence of users in the integrated circuit chip design and itsderivatives.

FIG. 1A is a diagram of an embodiment of a system 100 for illustrating apush operation. The system 100 includes a computing device N, a computernetwork 110, and an online design engineering system 102 (DES), where Nis an integer greater than zero.

Examples of a computing device, as used herein, includes a smart phone,a tablet, a computer, a desktop computer, a laptop computer, a smarttelevision, etc. Examples of the computer network 110 include a localarea network (LAN), such as an Intranet, and a wide area network (WAN),such as the Internet, or a combination of the LAN and WAN. Toillustrate, a communication protocol, such as Transmission ControlProtocol (TCP) over Internet Protocol (IP) or a Universal DatagramProtocol (UDP) over IP, is applied by computing devices, describedherein, to communicate via the computer network 110. To furtherillustrate, packets, such as TCP/IP or UDP/IP packets are generated by asending computing device and the packets are depacketized to extractdata within the packets by a receiving computing device.

Examples of the online design engineering system 102 include one or moreservers, or a combination of the one or more servers and one or moresearchable storage devices coupled to the one or more servers. In anembodiment, the online design engineering system 102 is implementedusing cloud computing, e.g., hardware virtualization, service-orientedarchitecture, etc. For example, the online design engineering system 102is a shared pool of computing resources, e.g., networks, servers,storage devices, computer software applications and services, etc. Toillustrate, the online design engineering system 102 includes a datacenter or a part of the data center that is used to process informationreceived from a computing device and send the processed information backto the computing device. The data center is a part of a cloud computingsystem and includes one or more servers that executes one or more tools,described below, to allow access to functionality of online designengineering processes, described herein, to computing devices. As such,a server is sometimes referred to herein as a cloud computing node thatis accessible to a computing device via the computer network 110 forexecuting one or more tools. In one embodiment, a combination of aserver and a searchable storage that is coupled to and accessed by theserver is sometimes referred to herein as a cloud computing node.

In an embodiment, a node is a virtual machine, which is an emulation ofa computer system. In the virtual machine, a hypervisor is a computersoftware or hardware or a combination thereof that shares and manageshardware resources, such as processors and memory devices, to executefunctions described herein as performed by the online design engineeringsystem 102. As an example, a virtual machine includes an operatingsystem, one or more application computer programs that run on top of theoperating system, and one or more hardware resources, such as centralprocessing units (CPUs), graphical processing units (GPUs), videoencoders, audio encoders, network communication devices, memory devices,internal communication devices, network communication devices, etc.,that are accessed by the one or more application computer programs viathe operating system and the hypervisor for performing the functionsdescribed herein as being performed by the online design engineeringsystem 102.

In an embodiment, the online design engineering system 102 is controlledby one or more design engineering entities. For example, the designengineering entity leases a space within a data center to provideservices, e.g., functions, etc., described herein as being performed bythe online design engineering system 102. The services are provided viathe computer network 110 to one or more computing devices that areconnected to the computer network 110.

In one embodiment, the online design engineering system 102 includes oneor more servers that perform the services described herein as beingperformed by the online design engineering system 102. In an embodiment,the online design engineering system 102 includes one or more processorsof one or more servers that perform the services described herein asbeing performed by the online design engineering system 102. As usedherein, a processor refers to an application specific integrated circuit(ASIC), or a programmable logic device (PLD), or a microprocessor, or acontroller, or a CPU.

A user N, e.g., a designer, etc., uses the computing device N to accessa user account N to generate a circuit design of an electrical circuitof a system on chip (SoC). For example, a user accesses a website thatis controlled by the design engineering entity, and provides user logininformation, such as an e-mail address or password or a combinationthereof, via the website to access a user account that is assigned tothe user by the online design engineering system 102. The website isaccessed to access multiple webpages of the website. Each webpage isused to display a corresponding account and to provide access to varioustools, described herein. An authenticator tool of the online designengineering system 102 determines whether the user login information isauthentic, such as matches data that is stored in a login database ofthe online design engineering system 102. Upon determining that the userlogin information is authentic, the user N is allowed by theauthenticator tool access to the user account N. On the other hand, upondetermining that the user login information is not authentic, the user Nis not allowed access by the authenticator tool to the user account N.Upon accessing the user account N, the user N creates the circuit designby accessing a circuit design tool, such as Ngspice™, or Cider™, orXspice™, which is executed by the online design engineering system 102.The design tool is not executed on the computing device N, which isoperated by the user N.

The circuit design created by the user N is sent from a networkinterface controller, such as a network interface card (NIC), of thecomputing device N via the computer network 110 to the online designengineering system 102 independent of whether a request for the circuitdesign is received by the online design engineering system 102. Forexample, there is no request made by a requester via a requestercomputing device and a requester account of the online designengineering system 102 to a user account of the online designengineering system 102 for the circuit design and the circuit design ispushed, such as sent without receiving the request, from the computingdevice N to the online design engineering system 102 via the computernetwork 110. As another example, at a time the user N indicates via theuser account N to upload the circuit design to the online designengineering system 102, the network interface controller applies acommunication protocol, e.g., TCP/IP or UDP/IP, etc., to the circuitdesign to generate one or more packets and sends the one or more packetsvia the computer network 110 to the online design engineering system 102for storage of the circuit design in a design database.

The online design engineering system 102 receives the circuit design viathe computer network 110 from the computing device N and processes thecircuit design to place the circuit design in a searchable storage ofthe online design engineering system 102. For example, the online designengineering system 102 applies the communication protocol to depacketizethe one or more packets that include the circuit design to obtain thecircuit design from the one or more packets, and stores the circuitdesign in the searchable storage. Any depacketization, described herein,as being performed by the online design engineering system 102 isperformed by an NIC of the online design engineering system 102. Itshould be noted that the circuit design is posted to the searchablestorage for access by other computing devices after obfuscating, e.g.,hiding, encrypting, etc., the circuit design so that the circuit designis not visible via user accounts, which are described below. The circuitdesign is not visible when accessed via the user accounts that do nothave a permission from the user N to view the circuit design. In anembodiment, the design engineering entity that creates and controls theonline design engineering system 102 is an operator, such as a manager,of the online design engineering system 102. For example, the circuitdesign when received by the online design engineering system 102 isposted on a webpage for access by other computing devices, e.g.,computing devices 1 through N−1, etc. The webpage is controlled by theoperator.

In an embodiment, none of the users 1 through N are employees of afabrication entity, as described herein, or a requester, or the designengineering entity. For example, none of the users 1 through N isemployed for wages or salary by an entity, such as a fabrication entity,or a requester, or the design engineering entity, to work full time orpart time for the entity.

FIG. 1B-1 is a diagram of an embodiment of a system 150 to illustrate apull operation. The system 150 includes the computing device N, arequester computing device 1, the computer network 110, and the onlinedesign engineering system 102. The online design engineering system 102includes a management server 152 and an automation certification (AC)server 112, both of which are further described below. Examples of arequester computing device include a computing device that is controlledby a requester, such as one or more entities that develop an integratedcircuit that includes one or more circuit designs. To illustrate, therequester is an entity that develops processors for performing graphicaloperations to generate graphics in computer games or other computersoftware applications. As another illustration, the requester is anentity that makes IoT devices. As yet another illustration, therequester is an entity that makes integrated circuits for applyingwireless communication protocols, such as Wi-Fi and Bluetooth. Otherexamples of the requester include an employee of the requester entity,or a user.

A requester accesses the website that is controlled by the designengineering entity, described below, and provides requester logininformation, such as an e-mail address or password or a combinationthereof, to access a requester account assigned to the requester by theonline design engineering system 102. The authenticator tool of theonline design engineering system 102 determines whether the requesterlogin information is authentic, such as matches data that is stored in alogin database of the online design engineering system 102. Upondetermining that the requester login information is authentic, therequester is allowed to access the requester account. On the other hand,upon determining that the requester login information is not authentic,the requester cannot access the requester account.

A requester 1 uses the requester computing device 1 to post via arequester account 1 a request for a design of the SoC to the onlinedesign engineering system 102 via the computer network 110. For example,the requester computing device 1 receives an input via an input deviceof the requester computing device 1 from the requester 1 via therequester account 1 to publish the request for the design of the SoConto a webpage of the online design engineering system 102. Examples ofan input device include a mouse, or a keyboard, or a keypad or atouchscreen display having one or more graphical display buttons. Therequester 1 that publishes the request is, in an embodiment, an employeeof a requester entity that controls the requester computing device 1and/or a contractor hired by the requester entity. The requestercomputing device 1 initiates the pull operation by providing the requestfor the design to the online design engineering system 102 via thecomputer network 110. As another example, a network interface controllerof the requester computing device 1 applies the communication protocolto the request for the design to generate one or more packets and sendsthe one or more packets via to the online design engineering system 102via the computer network 110. As used herein, an SoC is an integratedcircuit that integrates components of a computer or other electronicsystems, such as Internet of things (IoTs). For example, an SoC is anintegrated circuit that includes digital, or analog, or mixed signalfunctions. To illustrate, an SOC integrates a microcontroller and agraphics processing unit. As another illustration, an SOC integrates anoscillator with a phase-locked loop or integrates a voltage regulatorwith a power management circuit.

Upon receiving the one or more packets, the online design engineeringsystem 102 applies the communication protocol to depacketize the one ormore packets, and posts the request for the design onto a webpage thatis controlled by the design engineering entity that controls the onlinedesign engineering system 102. In response to the request, the onlinedesign engineering system 102 determines whether a design of theelectrical circuit that is created by the user N meets parametersindicated within the request. Examples of the parameters are providedbelow. Upon determining that the design of the electrical circuit meetsthe parameters, the online design engineering system 102 provides thedesign created by the user N via the computer network 110 to therequester computing device 1.

FIG. 1B-2 is a diagram of an embodiment of a system 111 to illustratecreations of designs D1 through Dn of different electrical circuitsbased on a variety of specifications S1 through Sn, where n is aninteger greater than zero. The system 111 includes the online designengineering system 102 and the requester computing device 1. Therequester computing device 1 is coupled to the online design engineeringsystem 102 via the computer network 110 of FIG. 1A.

The requester 1 accesses the website to further access the requesteraccount 1 via the requester computing device 1. The requester 1 furtherprovides an indication via the input device of the requester computingdevice 1 to provide a specification S1 including the parameters for adesign of an SoC. For example, a data sheet builder tool of the onlinedesign engineering system 102 receives the specification S1 via thecomputer network 110 from the requester computing device 1. Toillustrate, the data sheet builder tool applies the communicationprotocol to depacketize, such as parse, packets having the specificationS1 to extract the specification S1 from the packets. The packets aregenerated and sent from a network interface controller of the requestercomputing device 1. Upon receiving the indication, the management server152 accesses, such as reads, a data sheet from a template database, andsends the data sheet via the computer network 110 to the requestercomputing device 1. As an example, the data sheet is a template, such asa web form, that includes a plurality of fields for entry of parametersof a design. The template database is coupled to the management server152 and is a part of the online design engineering system 102. The datasheet is displayed on a display device of the requester computingdevice 1. Examples of a display device include a touch screen display, aliquid crystal display, a plasma display, and a light emitting diodedisplay. The requester 1 uses the input device of the requestercomputing device 1 to fill in the data sheet with the specification S1.The management server 152 receives the specification S1 via the computernetwork 110 and stores the specification S1 within a specification fileSF1 in a specification database 104. For example, the data sheet buildertool receives the specification S1 within a data sheet via the computernetwork 110 from the requester computing device 1, creates thespecification file SF1 within the specification database 104, and writesthe specification S1 to the specification file SF1. The specificationdatabase 104 is stored within a searchable storage 162 that is coupledto the management server 152. Similarly, the specification database 104stores multiple specification files SF2 through SFn. The specificationfile SF2 stores a specification S2 and similarly the specification fileSFn stores a specification Sn. The specification S2 is received from thesame requester 1 or from another requester via the computer network 110.An example of a searchable storage includes one or more memory devices,such as a read-only memory (ROM) or a random access memory (RAM) or acombination thereof. To illustrate, the searchable storage is a flashmemory or a redundant array of independent disks (RAID). Data storedwithin the memory devices is read by a read controller of the onlinedesign engineering system 102 and data is written via a write controllerof the online design engineering system 102 to the memory devices.

The management server 152, such as the data sheet builder tool, informsthe user 1 via the user account 1 and other users 2-N via correspondinguser accounts 2-N of receipt of the specification S1. For example, eachuser account 2-N is posted with information indicating that thespecification S1 is received and an identity, such as a name or therequester login information, of the requester 1. The users 1-N selectthe post via input devices of corresponding computing devices 1-Noperated by the users 1-N. Upon receiving the selection of the post fromthe user 1 via the user account 1, the management server 152, such asthe data sheet builder tool, accesses the specification S1 from thespecification database 104 and provides the specification S1 via theuser account 1 to the user 1. To illustrate, the data sheet builder toolreads the specification S1 of a data sheet from the specification fileSF1, applies the communication protocol to packetize the data sheethaving the specification S1 to generate packets, and sends the packetsvia the computer network 110 and the user account 1 to the usercomputing device 1 for display on the display device of the usercomputing device 1. Similarly, upon receiving the selection of the postfrom the user 2 via the user account 2, the management server 152, suchas the data sheet builder tool, provides the specification S1 via theuser account 2 to the user 2.

The user 1 uses the user computing device 1 to log into the user account1 to further access a circuit design tool 164 of design tools 158. Thecircuit design tool 164 is accessed remotely by a computing device tofacilitate generation of a design D1 based on the specification S1. Forexample, the management server 152 executes the circuit design tool 164to create a user interface, such as an image, on the computing device 1that is operated by the user 1. The user interface is displayed when thecircuit design tool 162 is executed by the management server 152. Theuser interface of the circuit design tool 162 includes circuit designgeneration graphics, such as graphics representing logic gates, graphicsrepresenting transistors, graphics representing connections between thelogic gates, and graphics representing logic between the transistors, togenerate the design D1. For example, upon receiving a selection of oneor more access buttons via the user account 1 and the computer network110, the management server 152 executes the circuit design tool 164 togenerate a display of the circuit design tool 164 on the user computingdevice 1 via the computer network 110. The selection of the one or moreaccess buttons is made by the user 1 via the input device of the usercomputing device 1. The user 1 generates a schematic of a circuit designby using the input device of the user computing device 1 to access thecircuit design tool 162. The management server 152 does not allow adownload of the circuit design tool 164 via the computer network 110 tothe computing device 1 operated by the user 1. For example, when thecircuit design tool 164 is accessed via the user account 1, there is nodisplay of a download button on the user computing device 1 fordownloading the circuit design tool 164. As such, the circuit designtool 164 is executed on the cloud computing node.

The design D1, such as a circuit schematic, is stored by the managementserver 152 within a design file DF1. For example, the circuit designtool 164 creates the design file DF1 within the searchable storage 162and stores, such as writes, the design D1 to memory addresses, withinthe searchable storage 162, designated to store the design file DF1. Itshould be noted that in one embodiment the design D1 is generatedindependent of whether a request for generation of the design D1 isreceived from the requester computing device 1 via the requester account1 and the computer network 110. A design file is generated by themanagement server 152, such as by the circuit design tool 164 or alayout design tool 166 of the design tools 158. The design file DF1 isstored within a design database 160, which is stored within thesearchable storage 162. For example, the user 1 operates the usercomputing device 1 to select an option to save the design D1. Uponreceiving an indication of the selection of the option to save via theuser account 1 and the computer network 110, the management server 152stores the design D1 within the design file DF1 and stores the designfile DF1 in the design database 160. Similarly, other designs D2-Dn arestored within corresponding design files DF2-DFn, which are stored inthe design database 160. The designs DF2-DFn are created by the user 1upon execution of the circuit design tool 164 or by another one of theusers 2-N upon execution of the circuit design tool 164.

Moreover, the user 1 uses the user computing device 1 to log into theuser account 1 to further access the layout design tool 166. The layoutdesign tool 166 is accessed to generate a layout design based on thespecification S1. For example, the management server 152 executes thelayout design tool 164 to create a user interface on the computingdevice 1 that is operated by the user 1. An example of a layout designtool is a computer program that is executed to generate multiple planes,such as IP layers, in which each plane includes tiles, such asrectangles. A tile is a cell that represents a portion of the electricalcircuit, such as n-type well or a p-type well or a via or aninterconnect between two components of the electrical circuit. As anillustration, Magic™ is an example of the layout design tool 166. Theuser interface is displayed when the layout design tool 166 is executedby the management server 152. For example, upon receiving a selection ofone or more access buttons via the user account 1 and the computernetwork 110, the management server 152 executes the layout design tool166 to generate a display of the layout design tool 166 on the usercomputing device 1 via the computer network 110. The layout design tool166 is executed for generation of the layout design. The selection ofthe one or more access buttons is made by the user 1 via the inputdevice of the user computing device 1. The user 1 generates the layoutdesign by using the input device of the user computing device 1 toaccess the layout design tool 166. The management server 152 does notallow a download of the layout design tool 166 via the computer network110 to the computing device 1 operated by the user 1. For example, whenthe layout design tool 166 is accessed via the user account 1, there isno display of a download button on the user computing device 1 fordownloading the layout design tool 166. As such, the layout design tool166 is executed on the cloud computing node.

The layout design is stored by the management server 152 within a layoutdesign file. The layout design file is stored within the design database160. For example, upon receiving via the computer network 110 aselection of a save button that is displayed upon execution of thelayout design tool 166, the layout design tool 166 creates a layoutdesign file within the searchable storage 162 and stores, such aswrites, the layout design to memory addresses, within the searchablestorage 162, designated to store the layout design file. It should benoted that in one embodiment the layout design is generated independentof whether a request for generation of the layout design is receivedfrom the requester computing device 1 via the requester account 1 andthe computer network 110. The save button is displayed on the displaydevice of the user computing device 1. Similarly, other layout designsare stored within corresponding layout design files, which are stored inthe design database 160. The other layout designs are created by theuser 1 upon execution of the layout design tool 166 or by another one ofthe users 2-N upon execution of the layout design tool 166. In oneembodiment, the layout design tool 166 that is provided access via theuser accounts 1 through N is stored within a layout design tool databasethat is controlled by and managed by the fabrication entity.

The design file DF1 is provided via the computer network 110 and therequester account 1 to the requester computing device 1 for a review ofcharacteristics of the design D1. Examples of the characteristics of acircuit design include components, such as transistors or logic gates,of the circuit design, connections between the components, and operationof the components of the circuit design. Similarly, the layout designfile is provided by the computer network 110 and the requester account 1for a review of characteristics of the layout design. Examples of thecharacteristics of a layout design include placement of tiles andconnections between the tiles, an order in which the planes are stacked,and a relative orientation in which the planes are stacked against eachother.

In one embodiment, the design file DF1 includes the layout designinstead of a circuit design. In an embodiment, the circuit design tool164 is referred to herein as a schematic design tool.

FIG. 1C-1 is a diagram to illustrate processes for verification of adesign and acceptance of the design by a requester, which is sometimesreferred to herein as a customer. In a process operation 1, the customeraccesses the requester account 1 to create a specification and fills inthe specification into a data sheet. The data sheet is created by thedata sheet builder tool, such as a computer program executed by themanagement server 152 of FIG. 1B-2. The management server 152 posts thedatasheet having the specification onto a webpage that is hosted by theonline design engineering system 102. In a process operation 2, one ormore of the users 1-N of a community access corresponding user accounts1-N to search for a project. For example, the user 1 provides a searchrequest to the online design engineering system for a project to designan SoC, such as an analog-to-digital converter or a digital to analogconverter or an oscillator. As another example, upon accessing thecorresponding user accounts 1-N, one or more of the users 1-N access thewebpage to view the specification. In a process operation 3, one or moreof the users 1-N generate one or more designs, such as a circuit designor a layout design, based on the specification and submit the designs tothe online design engineering system 102. For example, the user 1generates the circuit design D1 to satisfy the parameters of thespecification S1 and the user 2 generates the circuit design D2 to methe parameters of the specification S1. In such a manner, multiplesolutions for achieving the parameters of the specification S1 areprovided by the users 1 and 2.

In a process operation 4, the online design engineering system 102verifies the designs that are received from one or more of the users 1-Nvia corresponding user accounts 1-N. For example, upon receiving the oneor more designs via the corresponding user accounts 1-N, an onlineverification tool, such as a circuit design verification tool or alayout design verification tool, is executed by the management server152 to test the one or more designs. There is no need for reception bythe management server 152 from the one or more users 1-N viacorresponding user accounts 1-N of an indication for verifying the oneor more designs. However, in one embodiment, the indication forverifying the one or more designs is received to execute the onlineverification tool.

In a process operation 5, one or more designs that are created by theone or more users 1-N via corresponding user accounts 1-N and verifiedby the online design engineering system 102 are accepted by the customervia the requester account 1. Upon receiving an indication of theacceptance from the customer via the requester account 1, the managementserver 152 determines to reward, such as monetarily reward or provide ajob position or provide a contractual opportunity, one or more of theusers 1-N that created the one or more designs.

FIG. 1C-2 is a flowchart of an embodiment of an online designengineering method 113 for generating a design and providing therequester 1 access to the design. In an operation 115 of the method 113,the management server 152 receives a specification from the requester 1via the requester account 1 for production of the design of theelectrical circuit. The management server 152 receives the specificationvia the network interface controller of the requester computing device1, the computer network 110, and a network interface controller of theonline design engineering system 102.

In an operation 117 of the method 113, the management server 152provides access to the users 1-N via the corresponding user accounts 1-Nfor viewing the specification that is received in the operation 115. Forexample, after the users 1-N log into the corresponding user accounts1-N via corresponding computing devices 1-N, the user accounts 1-Nprovide a view on a display device of the corresponding computingdevices 1-N of a data sheet that includes the specification. One or moreof the users 1-N access the design tools 158 via the corresponding useraccounts 1-N to generate one or more designs, such as a circuit designor a layout design, of the electrical circuit based on the parameters ofthe specification received in the operation 115.

Moreover, in an operation 119 of the method 113, the management server152 provides access to the one or more designs of the electrical circuitvia the requester account 1 to the requester 1. The requester 1 viewsthe one or more designs of the electrical circuit to review thecharacteristics of the one or more designs to further determine whetherto accept or reject the one or more designs.

FIG. 1D is a diagram to illustrate fabrication of prototypes of an IPcircuit 170, an integrated circuit (IC) 172 or an IoT circuit 174. In anembodiment, multiple IP circuits are coupled to each other to create anintegrated circuit and multiple integrated circuits are coupled to eachother to create an IoT circuit. An example of an IP circuit is aregister or a flip-flop or a logic gate. An example of an integratedcircuit is an analog-to-digital converter, a digital to analogconverter, an encoder, a read controller, or a write controller, or aprocessor, or a memory device. An example of an IoT is a network circuitthat couples various Internet-connected things, such as cars orbuildings or temperature sensors or actuators, with each other via theInternet to enable the Internet-connected things to exchange data viathe Internet with each other.

A design of an SoC is created by the user 1 by accessing the designtools 158 of FIG. 1B-2 based on a specification. Moreover, the automaticcertification server 112 of FIG. 1B-1 performs a test on the design todetermine whether the design meets the parameters of the specification.Furthermore, the design of the SoC is stored in the searchable storage162 of FIG. 1B-2. The design stored in the searchable storage 162 issearchable by the requester 1 via the requester account 1 or via one ormore of the users 1-N via the corresponding user accounts 1-N. Forexample, a design is identified by its name, such as a series ofalphanumeric characters, that is assigned by the user who created thedesign or by a requester during submission of a data sheet forgenerating the design. Illustrations of the name of the design includesan analog-to-digital converter or an AND gate or an OR gate or an N-typetransistor or an encoder or a decoder. Another user or a requestersearches for the design based on the name of the design. To illustrate,the management server 152 generates a design search field, which isdisplayed on the computing device 1 operated by the user 1 or on therequester computing 1. The user 1 uses the user computing device 1 orthe requester 1 uses the requester computing device 1 to enter the nameof the design, such as a name of the electrical circuit, within thedesign search field. The management server 152 searches the designdatabase 104 of FIG. 1B-2 to determine whether there is a match betweenthe name of the design received from the user computing device 1 or therequester computing device 1 and a name of the design stored in thedesign database 104. Upon determining that there is a match, themanagement server 152 accesses, such as reads, the design, such as thedesign D1, from the design database 104 and provides the design D1 viathe computer network 110 to the user computing device 1 operated by theuser 1 via the user account 1 or to the requester computing device 1 viathe requester account 1 for review by the requester 1.

Moreover, there is no need for a nondisclosure agreement from thefabrication facility from a time the specification is received from therequester 1 to a time of generating a prototype of the electricalcircuit based on the design. For example, portions of the design areobfuscated by the management server 152, such as by an obfuscator tool,described below, before the design is accessed by one or more of theusers 2-N who did not create the design. To illustrate, when a layoutdesign is accessed by the user computing device N from a fabricationcomputing device via the computer network 110, the obfuscator toolobfuscates one or more Graphics Database System (GDS) layers of thelayout design before the layout design is stored in the searchablestorage 162.

Furthermore, the management server 152 generates a rating of the designbased on a number of times the design is used by one or more of theusers 2-N via corresponding user accounts 2-N. For example, themanagement server 152 keeps track of a number of times for which thedesign is displayed via the user accounts 2-N on the computing devices2-N. The rating of the design increases with an increase in the numberof times for which the design is displayed. Similarly, the rating of thedesign decreases with a decrease in the number of times for which thedesign is displayed. As another example, the management server 152calculates a number of times for which the design is bid on via the useraccounts 2-N on the computing devices 2-N. The rating of the designincreases with an increase in the number of times for which the designis bid on. Similarly, the rating of the design decreases with a decreasein the number of times for which the design is bid on. The managementserver 152 generates a bid field, which is displayed on the usercomputing device N via the computer network 110 and the user account N.The user N users the input device of the user computing device N toprovide a bid, such as a dollar amount, within the bid field. The bid issent from the user computing device N via the user account N and thecomputer network 110 to the management server 152. As yet anotherexample, the management server 152 computes a number of times for whichthe design is displayed via the user accounts 2-N is selected viacorresponding input devices of the computing devices 2-N. The rating ofthe design increases with an increase in the number of times for whichthe design is selected. Similarly, the rating of the design decreaseswith a decrease in the number of times for which the design is selected.

As another example, the management server 152 generates a rating of adesign and the rating is based on a number of times a comment, such as apositive comment or a negative comment, regarding the design is receivedfrom one or more of the users 2-N via corresponding user accounts 2-N.To illustrate, a field in which a post, such as a comment, is to beplaced is provided by the management server 152 via the computer network110 to display on the computing device 2 operated by the user 2. Theuser 2 uses the input device of the computing device 2 to select thefield and post the comment within the field. The comment is a positivecomment, such as one that praises functionality of the design oradvantages of the design, or a negative comment, such as one thatindicates disadvantages of the design or degrades the design. Upondetermining that a number of positive comments regarding the designposted via the user accounts 2-N exceeds a number of negative commentsregarding the design posted via the user accounts 2-N, the managementserver 152 increases the rating of the design. For example, as thenumber of positive comments regarding the design increases compared tothe number of negative comments, the management server 152 increases therating of the design. As another example, as a number of positivecomments regarding the design decreases compared to the number ofnegative comments, the management server 152 decreases the rating of thedesign.

In an embodiment, a combination of two or more of the number of timesfor which the design is displayed via the user accounts 2-N, the numberof times for which the design is bid on, the number of times for whichthe design is displayed via the user accounts 2-N is selected, thenumber of times for which a comment is made on the design are used bythe management server 152 to determine a rating of the design, a numberof tests that the design has passed, and a number of times for which thedesign is integrated in one or more integrated circuit chips. Forexample, a weighted combination of the rating generated based on thenumber of times for which the design is bid on and the rating generatedbased on the number of times for which a comment is made on the designis used by the management server 152 to generate a rating of the design.As another example, a weighted combination of the rating generated basedon the number of times for which the design has passed simulation testsand the rating generated based on the number of positive comments aremade on the design is used by the management server 152 to generate arating of the design.

The rating of the design is searchable via a rating search field that isgenerated by the management server 152 and is displayed via the useraccounts 1-N on the corresponding computing devices 1-N. For example,when the user 2 enters a name of the design within the rating searchfield displayed on a display device of the user computing device 2 andselects via the input device of the user computing device 2 a submitoption, such as a submit button, displayed on the display device, themanagement server 152 receives the name of the design via the computernetwork 110 from the computing device 2. The selection of the submitoption is an example of submission of a search request for a ratingassigned to the design. The management server 152 identifies, from thename of the design, a rating of the design that is stored within arating database of the searchable storage 162 of FIG. 1B-2, and providesthe rating via the computer network 110 and the user account 2 to thecomputing device 2.

In one embodiment, a specification is searchable via a specificationsearch field that is generated by the management server 152 and isdisplayed via the user accounts 1-N on the corresponding computingdevices 1-N. For example, the user 2 enters a name of the design withinthe specification search field displayed on a display device of the usercomputing device 2, and selects a submit option, such as a submitbutton, displayed on the display device. Upon selection of the submitoption, the management server 152 receives the name of the design viathe computer network 110 from the computing device 2. The managementserver 152 further identifies, from the name of the design, aspecification within the specification database 104 for generating thedesign of the electrical circuit, and provides the specification via thecomputer network 110 and the user account 2 to the computing device 2.

FIG. 1E is a diagram of an embodiment of a system 121. The system 121includes the requester computing device 1, the online design engineeringsystem 102 and fabrication computing devices 1 and 2. In one embodiment,a fabrication computing device and a requester computing device are thesame. In this embodiment, a requester is a fabrication entity.

The online design engineering system includes a server system 123, whichincludes the management server 152 and the automatic certificationserver 112 of FIG. 1B-1. The requester 1 uses the requester computingdevice 1 to access the website having a web address, such aswww.abcd.com. Upon accessing the website, the requester 1 logs into therequester account 1 to access a data sheet from the template database ofthe searchable storage 162 for providing a specification within the datasheet.

The user 1 also accesses the website via the user computing device 1.Upon accessing the website, the user 1 logs into the user account 1. Anotification indicating that the specification for a design is receivedby the management server 152 is posted within the user account 1. In oneembodiment, the user 1 enters a name of a design within thespecification search field to search for the specification that isreceived by the management server 152 and access the specification fromthe specification database 104. For example, the data sheet builder toolprovides the user account 1 with access to the specification to the usercomputing device 1 via the computer network 110. To illustrate, themanagement server 152 executes the data sheet builder tool to generate adisplay of a data sheet having the specification via the computernetwork 110 on a display device of the user computing device 1.Similarly, as another example, the management server 152 executes thedata sheet builder tool to generate a display of the data sheet havingthe specification via the computer network 110 on display devices of theuser computing devices 2 through N to provide access to thespecification to the user computing devices 2 through N.

Upon receiving the specification, the user 1 accesses a workspaceapplication 180 to further access the circuit design tool 164 togenerate a circuit design, such as a schematic, based on the parametersof the specification. For example, the workspace application 180 isexecuted by the management server 152 to provide access to the circuitdesign tool 164 on the user computer device 1 via the computer network110. As another example, the workspace application 180 is executed bythe management server 152 to generate a user interface on the displaydevice of the user computing device 1. The user 1 operates the inputdevice of the user computing device 1 to select a circuit design tooloption, such as a circuit design tool icon or a circuit design toolbutton, representing the circuit design tool 164 displayed on the userinterface. Upon receiving the selection of the circuit design tooloption via the computer network 110, the management server 152 providesaccess to the circuit design tool 164 via the computer network 110 andthe user account 1 to the user computing device 1. Moreover, a circuitdesign verification tool 188 is a computer program that is executed bythe automatic certification server 112 to test the circuit design todetermine whether the circuit design passes or fails the test. In oneembodiment, at a time the specification is received from the requestercomputing device 1, a test bench is generated by the management server152 for testing the circuit design. The same test bench is used by theautomatic certification server 112 to test the circuit design.

An obfuscator tool 182 is a computer program that is executed by themanagement server 152 to obfuscate one or more portions of the circuitdesign at a time when the circuit design is accessed from the searchablestorage 162 to provide the circuit design for display on the requestercomputing device 1 or on user computing devices 2-N via the website. Forexample, the user 2 accesses the website to log into the user account 2.Upon logging into the user account 2, the user 2 uses the user computingdevice 2 to request via the design search field the circuit design byproviding a name of the circuit design within the design search field.The obfuscator tool 182 of the management server 152 accesses thecircuit design from the searchable storage 162 and obfuscates one ormore portions of the circuit design to generate an obfuscated circuitdesign and sends the obfuscated circuit design via the computer network110 and the user account 2 to the computing device 2. In one embodiment,in addition to sending the obfuscated circuit design, the managementserver 152 sends a data sheet including a specification for generatingthe design via the computer network 110 and the user account 2 to theuser computing device 2.

The user 1 further accesses the layout design tool 166 via the workspaceapplication 180 to generate a layout design based on the circuit design.For example, the workspace application 180 is executed by the managementserver 152 to generate a user interface on the display device of theuser computing device 1. The user 1 operates the input device of theuser computing device 1 to select a layout design tool option, such as alayout design tool icon or a layout design tool button, representing thelayout design tool 166 displayed on the user interface. Upon receivingthe selection of the layout design tool option via the computer network110, the management server 152 provides access to the layout design tool166 via the computer network 110 and the user account 1 to the usercomputing device 1. Moreover, a layout design verification tool 190 is acomputer program that is executed by the automatic certification server112 to test the layout design to determine whether the layout designpasses or fails the test. Upon determining that the circuit designpasses the test and the layout design passes the test, the managementserver 152 sends the circuit design, the layout design, and thespecification to the fabrication computing device 1 that is controlledby a fabrication facility for fabrication of a prototype of an SoC.

FIG. 1F is a diagram of an embodiment of a system 125 to illustrate afabrication of a prototype of a design that is created and verifiedusing the online design engineering system 102. The system 125 includesthe server system 123, the searchable storage 162 and the fabricationcomputing device 1, which is coupled via the computer network 110 withthe server system 123.

The server system 123 includes the obfuscator tool 182, the workspaceapplication 180, a design simulation report generator tool 184, and adesign rating generator tool 192. Each of the design simulation reportgenerator tool 184 and the design rating generator tool 192 is acomputer program that is executed by the server system 123.

Upon receiving a specification from the requester 1 via the requesteraccount 1, the management server 152 posts a competition for generatinga design of the electrical circuit based on a specification. The user 1uses the user computing device 1 to access the workspace application 180via the computer network 110 and the user account 1 to further accessthe circuit design tool 164. The circuit design tool 164 is accessed bythe user 1 to generate a schematic 1830 of a circuit design according tothe specification. An example of the schematic 1830 includes multiplecomponents, such as transistors, logic gates, resistors, inductors, orcapacitors, that are coupled to each other, such as in series orparallel, and connections between the components of the electricalcircuit. The automatic certification server 112 of the server system 123executes a local test bench tool 165 to generate a local test bench,such as one or more power sources that are coupled to input pins of theschematic 1830 and one or more loads that are coupled to the output pinsof the schematic 1830. An example of a load includes a resistor or acapacitor or an inductor. In one embodiment, the local test bench isgenerated by the automatic certification server 112 or by the managementserver 152 at a time of reception, by the management server 152, of thespecification based on which the schematic 1830 is generated. A localcircuit design test is executed by the automatic certification server112 when the user 1 selects, via the user account 1, one or more buttonsdisplayed by the workspace application 180 on the display device of theuser computing device 1 to apply the local test bench tool 165 on theschematic 1830. When the local circuit design test is executed, resultsof the local circuit design test are generated by the automaticcertification server 112 to determine whether the schematic 1830 passesor fails the local circuit design test. In an embodiment, the local testbench tool 165 is stored within a memory device of the user computingdevice 1 and is executed by a processor of the user computing device 1instead of being stored in the searchable storage 162 and executed bythe automatic certification server 162.

The schematic 1830 and results of application of the local test benchtool 165 are stored in the searchable storage 162. Moreover, in anembodiment, the schematic 1830 is stored in a directory that isaccessible via the workspace application 180 and the user account 1 tothe user 1. The directory is stored on the computing device 1 that isoperated by the user 1.

Furthermore, the automatic certification server 112 executes the circuitdesign verification tool 188 to perform a test on the schematic 1830 todetermine whether the schematic 1830 passes or fails the test. Resultsof the test that are applied by executing the circuit designverification tool 188 are stored in the searchable storage 162. Forexample, a data sheet is updated by the automatic certification server112 to include the results of the test of the schematic 1830 applied byexecuting the circuit design verification tool 188. Upon determiningthat the schematic 1830 passes the test executed by the circuit designverification tool 188, the schematic 1830 is indicated by the automaticcertification server 112 to be certified by the design engineeringentity. The certification by the design engineering entity is a resultof an official characterization of the schematic 1830. An example of theofficial characterization is an execution of the circuit designverification tool 188 under control of the design engineering entity.The circuit design verification tool 188 is executed under control ofthe design engineering entity. For example, an employee of the designengineering entity uses the computing device 2 to execute the circuitdesign verification tool 188. The automatic certification server 112does not allow a download of the circuit design verification tool 188via the computer network 110 to the user computing device 1 operated bythe user 1. As such, the circuit design verification tool 188 isexecuted on the cloud computing node.

In one embodiment, in addition to the execution of the local circuitdesign test and the circuit design verification tool 188, one or more ofthe user accounts 2-N are provided access by the management server 152to the schematic 1830 for performing a community circuit designverification test. Before the one or more of the users 2-N access theschematic 1830, the obfuscator tool 182 obfuscates one or more portionsof the schematic 1830. As such, there is no need for a nondisclosureagreement between one or more of the users 2-N and the user 1 thatcreated the schematic 1830.

To perform the community circuit design verification test, one or moreof the users 2-N access via the corresponding user accounts 2-N thecircuit design verification tool 188 or the local test bench tool 165 ora local circuit verification tool that is stored in the correspondingcomputing device 2-N to test the schematic 1830. The local circuitverification tool is executed by a processor of corresponding computingdevice 2-N. Results of application of the community circuit designverification test by the users 2-N of the community are stored in thesearchable storage 162.

Based on the results of the use of the local test bench tool 165 by theuser 1 via the user account 1, the application of the circuit designverification tool 188 by the automatic certification server 112, and/orthe local circuit verification tool used by one or more of the users2-N, the user 1, such as person A, and/or other users, such as person Band person C, are determined by the management server 112 to be winnersof the competition for generating a circuit design of the electricalcircuit. For example, the management server 152 determines that theschematic 1830 created by the user 1, and other schematics created bythe other users to meet the specification passes the local circuitdesign test applied using the local test bench tool 165, the testapplied by executing the circuit design verification tool 188, and/orpasses the test applied by executing the local circuit verification toolamong multiple schematics received from the users 1-N based on thespecification.

In an embodiment, results of the application of the local test benchtool 165 by the user 1 via the user account 1, the application of thecircuit design verification tool 188 by the automatic certificationserver 112, and/or the application of the local circuit verificationtool used by one or more of the users 2-N are stored within a datasheet. The data sheet with the results is sent from the managementserver 152 via the computer network 110 to the requester computingdevice 1 for access via the requester account 1.

In one embodiment, the circuit design verification tool 188 is the sameas the local test bench tool 165 and/or the local circuit verificationtool. For example, the user 1, the users 2-N, and the design engineeringentity apply the same tool for verifying the schematic 1830.

The user 1 further uses the computing device 1 to access the workspaceapplication 180 via the computer network 110 and the user account 1 tofurther access the layout design tool 166 from the online designengineering system 102. The layout design tool 166 is accessed by theuser 1 via the user computing device 1 and the user account 1 togenerate a layout design 127 that is based on the schematic 1830 and thespecification. The automatic certification server 112 of the serversystem 123 executes a local layout verification tool 167, such as onefor measuring physical dimensions of each cell within a plane, physicaldimensions of each plane, an orientation of the planes with respect toeach other, and an order of arrangement of the planes with respect toeach other. The local layout verification tool 167 is executed by theautomatic certification server 112 when the user 1 selects one or morebuttons displayed by the workspace application 180 to apply the locallayout verification tool 167 on the layout design 127. When the locallayout verification tool 167 is executed, results of the execution aregenerated by the automatic certification server 112 to determine whetherthe layout design 127 passes or fails a local layout design test. In anembodiment, the local layout verification tool 167 is stored within amemory device of the user computing device 1 and is executed by aprocessor of the user computing device 1 instead of being stored in thesearchable storage 162 and executed by the automatic certificationserver 162.

The layout design 127 and results of application of the local layoutdesign test are stored in the searchable storage 162. Moreover, in anembodiment, the layout design 127 is stored in a directory that isaccessible via the workspace application 180 and the user account 1 tothe user 1. The directory, in which the layout design 180 is stored, isstored on the computing device 1 that is operated by the user 1.

Furthermore, the automatic certification server 112 executes the layoutdesign verification tool 190 to perform a test on the layout design 127to determine whether the layout design 127 passes or fails the test.Results of the test that are applied by executing the layout designverification tool 190 are stored in the searchable storage 162. Forexample, a data sheet is updated by the automatic certification server112 to include the results of the test of the layout design 127. Upondetermining that the layout design 127 passes the test executed by thelayout design verification tool 190, the layout design 127 is indicatedby the automatic certification server 112 to be certified by the designengineering entity. The certification by the design engineering entityis a result of an official characterization of the schematic 1830. Anexample of the official characterization is an execution of the layoutdesign verification tool 190 under control of the design engineeringentity. The layout design verification tool 190 is executed undercontrol of the design engineering entity. For example, an employee ofthe design engineering entity uses the computing device 2 to execute thelayout design verification tool 190. The automatic certification server112 does not allow a download of the layout design verification tool 190via the computer network 110 to the computing device 1 operated by theuser 1. As such, the layout design verification tool 190 is executed onthe cloud computing node.

In one embodiment, in addition to the execution of the local layoutdesign test and the layout design verification tool 190, one or more ofthe user accounts 2-N are provided access by the management server 152to the layout design 127 for performing a community layout designverification test. Before the one or more of the users 2-N access thelayout design 127, the obfuscator tool 182 obfuscates, such as hides orcovers, one or more portions of the layout design 127. As such, there isno need for a nondisclosure agreement between one or more of the users2-N and the user 1 that created the layout design 127.

To perform the community layout design verification test, one or more ofthe users 2-N access the layout design verification tool 190 or thelocal layout verification tool 167 or a local layout verification toolthat is stored in the corresponding computing device 2-N via thecorresponding user accounts 2-N to test the layout design 127. The locallayout verification tool 167 is executed by the processor ofcorresponding computing device 2-N. Results of application of thecommunity layout design verification test by the users 2-N of thecommunity are stored in the searchable storage 162.

Based on the results of the use of the local layout verification tool167 by the user 1 via the user account 1, the application of the layoutdesign verification tool 190 by the automatic certification server 112,and/or the local layout verification tool used by one or more of theusers 2-N, person A and person B from person A, person B, and person Care determined by the management server 112 to be winners of thecompetition for generating a layout design of the electrical circuit.For example, the management server 152 determines that the layout design127 created by person A and other layout designs created by person B tomeet the specification passes the local layout design test, the testapplied by executing the layout design verification tool 190, and/orpasses the test applied by executing the local layout verification toolamong multiple layout designs received from person A, person B, andperson C and generated based on the specification.

In an embodiment, the results of the application of the local layoutdesign test by the user 1 via the user account 1, the application of thelayout design verification tool 190 by the automatic certificationserver 112, and/or the application of the local layout verification toolused by one or more of the users 2-N are stored within a data sheet. Thedata sheet with the results is sent from the management server 152 viathe computer network 110 to the requester computing device 1 for accessvia the requester account 1.

The management server 152 accesses a Graphics Database System II (GDSII)file having the layout design 127 from the searchable storage 162,accesses a design file having the schematic 1830, and accesses aspecification file having the specification for generating the layoutdesign 127 from the searchable storage 162 and provides the GDSII file,the design file, and the specification file to the fabrication computingdevice 1 via the computer network 110. It should be noted that GDSII isa database file format for data exchange of a layout of the electricalcircuit. GDSII is a binary file format representing planar geometricshapes, text labels and other information about the layout design 127 ina hierarchical form. The fabrication facility fabricates a prototype ofthe electrical circuit from the layout design 127 of the GDSII file.

In one embodiment, the local test bench tool 165, the circuit designverification tool 188, the layout design verification tool 190, and/orthe local layout verification tool 167 are portions or parts of thedesign simulation report generator tool 184.

FIG. 2 is a diagram of an embodiment of a system 200 for illustratingthe online design engineering system 102 in communication, via thecomputer network 110, with multiple user computing devices 1-N that areoperated by the users 1-N and requester computing devices 1 and 2 thatare operated by corresponding requesters 1 and 2. The system 200includes the computing device N and additional computing devices 1, 2,through N−1. For example, each of the computing device 1 thru N−1 isoperated by a different designer. To illustrate, the computing device 1is operated by the user 1, the computing device 2 is operated by theuser 2, and so on until the computing device N is operated by the userN. In an embodiment, each user 1 through N is a designer of a circuitdesign. For example, the user 1 designs a different circuit design thanthe user 2. The computing devices 1 through N are connected to thecomputer network 110. For example, each of the computing devices 1through N includes a network interface controller for communicatingpacketized data to the computer network 110.

The system 200 further includes the online design engineering system102, which includes various databases, e.g., a circuit design tooldatabase 206 in which the circuit design tool 164 of FIG. 1B-2 isstored, a layout design tool database 208 in which the layout designtool 166 of FIG. 1B-2 is stored, a prototype development systemsdatabase 210, the design database 160, the specification database 104, acomment database 204, and a public-private indicator database 220. Eachdatabase is stored within one or more memory devices of the searchablestorage 162. For example, the circuit design tool database 206 is storedin one or more memory devices and the specification database 104 isstored in one or more memory devices.

The circuit design tool database 206 stores rules and tools forgenerating a circuit design schematic. For example, the circuit designtool database 206 stores a computer program for generating a graphicalrepresentation, e.g., a schematic, etc., of a circuit design. As anotherexample, the circuit design tool database 206 stores a computer programfor generating a code that is executed to generate the schematic. Eachcomponent of a circuit design abides by one or more design rules. Forexample, an AND gate has an output and two inputs. As another example,an OR gate's output is high if any of its inputs are high, e.g., a bit1, etc. The circuit design tool database 206 includes other rules forother components, e.g., transistors, diodes, multiplexers, flip-flops,capacitors, inductors, resistors, etc., of a circuit design.

The layout design tool database 208 stores rules regarding how to formand arrange various IP layers of a layout design of the SoC. Forexample, the layout design tool database 208 includes identities ofcomponents of each plane, a manner of connecting the components, and amanner of connecting the planes with each other. As another example, thelayout design tool database 208 stores how various IP layers, such as asubstrate layer, and a gate layer, of a layout design are to be arrangedwith respect to each other. As yet another example, the layout designtool database 208 stores a type of doping, such as n-type or p-type tobe applied to a substrate, a number of vias between two adjacent ornon-adjacent layers of a layout design, a number of traces betweencircuit components formed on an IP layer of the layout design, a numberof pin outs of the layout design, and a number of pin ins of the layoutdesign. In an embodiment, the layout design tool database 208 isgenerated by one or more fabrication entities and sent via the computernetwork 110 for storage within the online design engineering system 102.In one embodiment, the layout design tool database 208 is controlled bya fabrication entity and is accessible via the online design engineeringsystem 102. The layout design tool database 208 is not stored within theonline design engineering system 102 but within a cloud computing nodethat is under control of, such as leased by or owned by, a fabricationentity. When a user gains access to the online design engineering system102, the user is allowed access by the management server 152 to thelayout design tool database 208.

The prototype development systems database 210 stores a computer programfor testing a prototype of the electrical circuit. For example, aprototype of an integrated circuit in which a layout design isimplemented is connected to a computer, such as a user computer or afabrication entity computer, via a cable, such as a serial transfercable, a parallel transfer cable, or a universal serial bus (USB) cable.When the prototype is connected to the computer, a request for executionof a validation test on the prototype is sent from the computer via anaccount, such as the user account 1 or a fabrication entity account 1,and the computer network 110 to the prototype tester and test reportgenerator tool of the online design engineering system 102. For example,the user 1 selects, via the input device of the user computing device 1,a button displayed within the user account 1 to generate and send therequest for execution of the validation test. Upon receiving therequest, the management server 152 provides the computer with access tothe prototype tester and test report generator tool. The prototypetester and test report generator tool is executed by the automaticcertification server 112 to provide an input value to the prototype forprocessing of the input value by the prototype. The prototype isimplemented on a printed circuit board (PCB) during a test conducted bythe prototype tester and test report generator tool. The PCB is coupledto the computer for testing the prototype. The prototype tester and testreport generator tool receives results of the processing from theintegrated circuit via the cable and the computer network 110, anddetermines whether the results match pre-determined values. Upondetermining that the results match the pre-determined values, theprototype tester and test report generator tool determines that theprototype passes the validation test. On the other hand, upondetermining that the results do not match the pre-determined values, theprototype tester and test report generator tool determines that theprototype fails the validation test. The results of the validation test,such as the prototype passed the validation test, the prototype failedthe validation test, and output voltage values generated during thevalidation test, are integrated by the data sheet builder tool within adata sheet that includes a specification based on which the design forthe prototype is generated. For example, the data sheet is integratedwith pass or fail and values, such as voltage values or current values,that are output when the input value is provided to the prototype. Thedata sheet builder tool sends the data sheet including the results ofthe test of the prototype via the computer network 110 to the requestercomputing device 1 via the requester account 1. It should be noted thatthe prototype tester and test report generator tool is not downloaded tothe computer. Rather, the prototype tester and test report generatortool is executed by the management server 152.

A fabrication entity uses a fabrication computing device to access afabrication entity account to access the online design engineeringsystem 102. For example, a fabrication entity accesses the website andprovides fabrication entity login information, such as an e-mail addressor password or a combination thereof, via the website to access afabrication entity account that is assigned to the fabrication entity bythe online design engineering system 102.

The design database 160 circuit designs of various electrical circuitsthat are created by the users 1 through N. For example, the managementserver 152 receives circuit design schematics from the computing devices1 through N via the computer network 110 and stores the circuit designschematics within the design database 160. As another example, themanagement server 152 receives layout designs of various electricalcircuits from the computing devices 1 through N via the computer network110 and stores the layout designs within the design database 160.

The specification database 104 stores specifications of variouselectrical circuits. For example, the specification database 104includes textual data and/or graphical data describing restrictions onvarious electrical parameters, such as amounts of input voltages,amounts of input currents, amounts of output currents, amounts of outputvoltages, frequencies of operation, or lack of use of a clock signal,and on various physical parameters, such as a number of pin ins, anumber of pin outs, and use or lack of use of a clock signal pin, ofvarious electrical circuits of one or more SoCs. As another example, thespecification database 104 includes textual data and/or graphical dataidentifying a type, such as a name or an identifier, of the electricalcircuit, such as a buffer, an inverter, a logic gate, a half-adder, afull adder, a processor, an analog-to-digital converter, or adigital-to-analog converter.

The comment database 204 stores comments or posts made by the users 1through N via the corresponding user accounts 1 through N regardingvarious designs. For example, the user 1 logs into the user account 1 toaccess the user account 1 from an account server 212 via the computernetwork 110, and posts a comment to the user account 1. The user 1 usesthe user computing device 1 to provide via the user account 1authorization to the management server 152 to allow one or more of theother users 2 through N to access the comment via the corresponding useraccounts 2 through N. The one or more of the other users 2 through Naccess their corresponding user accounts 2 through N to view thecomment.

In an embodiment, a user or a requester or a fabrication entity provideslogin information, e.g., name, password, biometric information, etc., tothe online design engineering system 102 to access his/her/its account.An example of a requester is a user that is an employee of the requesterentity or is a contractor hired by the requester entity. Upon receivingthe login information, an authenticator tool of the online designengineering system 102 compares the login information with pre-storedlogin information to determine whether the login information matches thepre-stored login information. The user or the requester or thefabrication entity is provided access to his/her/its account by theauthenticator tool upon determining that the login information matchesthe pre-stored information. Otherwise, the user or the requester or thefabrication entity is not provided access to his/her account in case ofa mismatch between the login information and the pre-stored information.A user or the requester or the fabrication entity logs into his/her/itsaccount to access one or more databases of the online design engineeringsystem 102 such as the circuit design tool database 206, the layoutdesign tool database 208, the prototype development systems database210, the design database 160, the specification database 104, and thecomment database 204. Without being authenticated, the authenticatortool of the online design engineering system 102 does not provide accessto any of the databases. The user accounts 1 through N assigned to thecorresponding users 1 through N by the authenticator tool, fabricationentity accounts 1 and 2 assigned to fabrication entities 1 and 2 by theauthenticator tool, and requester accounts 1 and 2 of the correspondingrequesters 1 and 2 are stored within the account server 212, which iscoupled to the management server 152.

The system 200 includes the requester computing devices 1 and 2 that areconnected to the online design engineering system 102 via the computernetwork 110. Moreover, the system 200 includes the fabrication computingdevices 1 and 2 that are connected via the computer network 110 to theonline design engineering system 102. The one or more fabricationcomputing devices 1 and 2 are controlled by the correspondingfabrication entities 1 and 2. As an example, the fabrication entities 1and 2 are corporations that fabricate a prototype of the electricalcircuit.

FIG. 3 is a diagram of an embodiment of various tools of the onlinedesign engineering system 102. It should be noted that in an embodiment,the online design engineering system 102 provides a specification drivendesign process, a web driven data sheet such as an online data sheet, acommunity driven interactive specification builder, a community-basedverification of a circuit design, a pooling of knowledge of thecommunity, a continual improvement through community input such ascomments on a circuit design, a verification independent of a designer,an optional physical validation flow, test chip runs for validation of acircuit design, electrical characterization of test chips by the designengineering entity, feedback from the community, a rating of designerskills, a rating of a circuit design, a count of a number of uses of acircuit design, circuit design specific forms, a simulation of allspecification parameters on the data sheet by using a simulationsoftware, verification by the design engineering entity of all thespecification parameters on the data sheet, coupling of a circuit designwith a glue logic design or another integration circuit design providedby the design engineering entity, tools for generation ofmanufacturing-aware electronic models that are sent to the fabricationentities 1 and 2, manufacturing on a shuttle, testing of an integratedcircuit chip design using a test printed circuit board and softwareprovided by the design engineering entity, and/or reports or resultsprovided by the community based on experience, etc. The reports andresults provide potential for revenue sharing based on additionalspecification parameters that are checked.

The online design engineering system 102 includes an access manager tool303, a royalty generator tool 304, the obfuscator tool 182, a rewardgenerator tool 316, a data sheet builder tool 318, a specificationcompleteness checker tool 302, a specification compliance checker tool320, a design searcher tool 322, a derivative generator tool 324, aprototype tester and test report generator tool 306, a shuttle managertool 404, a use counter tool 312, the design simulation report generatortool 184, a design competition generator tool 310, a designer ratinggenerator tool 326, the design rating generator tool 192, a designproject searcher tool 328, a public-private indicator tool 329, aproject poster tool 330, the authenticator tool 332, and a designserving manager tool 402. In one embodiment, a tool, as used herein, isa hardware, such as an ASIC or a PLD, or a software, such as a computerprogram, executed by a processor, or a combination of the hardware andsoftware. For example, a tool is a computer software program that isexecuted by one or more processors of a server. As another example, atool is an ASIC or a PLD. As an example, the access manager tool 303,the royalty generator tool 304, the obfuscator tool 182, the rewardgenerator tool 316, the data sheet builder tool 318, the specificationcompleteness checker tool 302, the specification compliance checker tool320, the design searcher tool 322, the derivative generator tool 324,the shuttle manager tool 404, the use counter tool 312, the designcompetition generator tool 310, the designer rating generator tool 326,the design rating generator tool 192, the design project searcher tool328, the project poster tool 330, the authenticator tool 332, the designserving manager tool 402, and the public-private indicator tool 329 areparts of or executed by the management server 152. Moreover, as anexample, the prototype tester and test report generator tool 306 and thedesign simulation report generator tool 184 are parts of or executed bythe automatic certification server 112. In an embodiment, any tool ofthe online design engineering system 102 is coupled to any other tool ofthe online design engineering system 102 via a communication medium,such as a conductor for transferring data serially, multiple conductorsfor transferring data in a parallel manner, or a universal serial bus.

The access manager tool 303 determines whether to provide a computingdevice, such as, a user computing device or a requester computing deviceor a fabrication computing device, with access to other tools and theworkspace application 180. Examples of the other tools include theroyalty generator tool 304, the obfuscator tool 182, the rewardgenerator tool 316, the data sheet builder tool 318, the specificationcompleteness checker tool 302, the specification compliance checker tool320, the design searcher tool 322, the derivative generator tool 324,the shuttle manager tool 404, the use counter tool 312, the designcompetition generator tool 310, the designer rating generator tool 326,the design rating generator tool 192, the design project searcher tool328, the project poster tool 330, the design serving manager tool 402,the public-private indicator tool 329, the prototype tester and testreport generator tool 306, and the design simulation report generatortool 184 of the online design engineering system 102. For example, theaccess manager tool 303 determines whether login information that isreceived from the computing device via the computer network 110 isauthenticated by the authenticator tool 332. To illustrate, the accessmanager tool 303 sends a request to the authenticator tool 332 todetermine whether the login information is valid. Upon receiving a replyfrom the authenticator tool 332 that the login information is valid, theaccess manager tool 303 provides access to the computing device to theother tools of the online design engineering system 102 and theworkspace application 180. On the other hand, upon receiving a replyfrom the authenticator tool 332 that the login information is invalid,the access manager tool 303 denies access to the computing device to theother tools of the online design engineering system 102 and theworkspace application 180. In one embodiment, the access manager tool303 provides online access via the computer network 110 to the othertools and the workspace application 180 but does not allow a download ofone or more of the other tools and the workspace application 180 to thecomputing device from the online design engineering system 102 via thecomputer network 110.

The royalty generator tool 304 generates royalties, such as, in terms ofpercentages or monetary amounts, for designs that are created by theusers 1 through N and that passes one or more of the local circuitdesign test, the test executed by the circuit design verification tool188, the community circuit design verification test, the local layoutdesign test, the test executed by the layout design verification tool190, and the community layout design verification test. For example, theroyalty generator tool 304 generates a royalty amount or a royaltypercentage when a designer posts a schematic of a circuit design tohis/her user account and the schematic passes one or more of the localcircuit design test, the test executed by the circuit designverification tool 188, the community circuit design verification test.As another example, the royalty generator tool 304 generates a royaltyamount or a royalty percentage when a designer posts a layout design tohis/her user account and the layout design passes one or more of locallayout design test, the test executed by the layout design verificationtool 190, and the community layout design verification test. As yetanother example, the royalty generator tool 304 generates a royaltyamount or a royalty percentage for a design based on a number of uses ofthe design. The royalty generator tool 304 accesses the number of usesfrom the use counter tool 312 for multiple designs. Upon determiningthat a number of uses of a first one of the designs is greater than anumber of uses of a second one of the designs, the royal generator tool304 generates a higher amount of royalty for accessing the first designthan that for accessing the second design. In one embodiment, a royaltyamount or a royalty percentage is provided from the royalty generatortool 304 to the requester 1 via the requester computing device 1 and therequester account 1 when a design for which the royalty percentage orthe royalty amount is calculated is accessed by the requester computingdevice 1 via the requester account 1. For example, the requester 1 usesthe requester computing device 1 to access the request account 1 tofurther request access to a design, such as via the design search field.Upon receiving the request for access, the royalty generator tool 190provides access to the design with a royalty amount or a royaltypercentage for accessing the design.

In an embodiment, the royalty generator tool 304 is connected to acredit and debit server system via the computer network 110. Forexample, when the requester 1 sends a request via the requester account1 for a circuit design to the online design engineering system 102, anda designer provides the circuit design to the requester via the onlinedesign engineering system 102, the royalty generator tool 304 provides aroyalty, such as a royalty amount or a royalty percentage, to the creditand debit server system, and the credit and debit server system debitsthe royalty from a deposit account of the requester and credits theamount to a deposit account of the designer. A deposit account ismaintained by the credit and debit server system.

The obfuscator tool 182 hides at least a portion of a design so that aneed for a non-disclosure agreement (NDA) between the requester and adesigner is avoided. For example, the obfuscator tool 182 overlays aschematic or a layout design with an opaque portion, such as an opaqueblock, an opaque shape, that hides one or more portions of the schematicor one or more portions of the layout design to create a black box. Toillustrate, pin ins and pin outs of the schematic are not covered by theopaque portion. To further illustrate, power pins, ground pins, datainput pins, and data output pins are not covered or hidden to create theblack box. In one embodiment, one or more pin ins and/or one or more pinouts of the schematic are covered or hidden by the opaque portion. Asanother example, the obfuscator tool 182 conceals various IP layers of alayout design and conceals various tiles of the IP layers to create ablack box. In this example, pin ins and pin outs of the layout designare not covered by the opaque portion. In one embodiment, one or morepin ins and/or one or more pin outs of the layout design are covered bythe opaque portion.

The obfuscator tool 182 is coupled to the authenticator tool 332 fordisplaying a design to a user or a requester with permission andobfuscating one or more portions of the design before display the designto the user or the requester without permission. For example, when anaccount, such as the user account 1 or the requester account 1, haspermission from the authenticator tool 332 to display a design on acomputing device, the obfuscator tool 182 does not overlay the designwith the opaque portion to display the design on the computing device.In addition to providing access to the design to a computing device,such as a user computing device or a requester computing device, via thecomputer network 110, the management server 152 sends a data sheetincluding a specification for generating the design via the computernetwork 110 to the computing device. The design is provided access viaan account, such as a user account or a requester account. Theauthenticator tool 332 determines that the account of another user orthe requester has permission to view the design when a designerindicates via his/her account that the design is public. On the otherhand, when the authenticator tool 332 determines that the account ofanother user, other than the designer, or the requester does not havepermission to display the design on the computing device, the obfuscatortool 182 overlays the design with the opaque portion to generate anobfuscated design. In addition to providing access to the obfuscateddesign to the computing device, such as the user computing device or therequester computing device, via the computer network 110, the managementserver 152 sends a data sheet including a specification for generatingthe design via the computer network 110 to the computing device. Theobfuscated design is provided access via the account, such as the useraccount or the requester account. The authenticator tool 332 determinesthat the account does not have permission to view the design when theuser or the requester indicates via his/her account that the design isprivate.

In one embodiment, the obfuscator tool 182 accesses the public-privateindicator database 220 of the searchable storage 162 to determine anassociation between an account, such as a requester account or a useraccount, and an indication of whether a design is public or private. Thepublic-private indicator database 220 stores a list of associations,such as, a one-to-one mapping or a correspondence or a uniquerelationship or a link, between various accounts and indications ofwhether the accounts are allowed to access the design withoutobfuscation. For example, a first entry in the list indicates that theuser 1 via the user account 1 has indicated that a design 1 of theelectrical circuit be private to the user account 2. The user 1 createsthe design 1 via the user account 1. Moreover, a second entry in thelist indicates that the user 1 has indicated via the user account 1 thatthe design 1 be private to the requester account 2. Also, a third entryin the list indicates that the user 1 has indicated via the user account1 that the design 2 be public to the user account 2. The obfuscator tool182 accesses the first entry in response to an indication received fromthe user computing device 2 for accessing via the user account 2 and thecomputer network 110 the design 1 and obfuscates one or more portions ofthe design 1 to generate an obfuscated design. For example, when thedesign searcher tool 322 receives a request via the computer network 110and the user account 1 from the user computing device 1 for accessing adesign stored within the design database 160, the design searcher tool322 sends a signal to the obfuscator tool 182 of the request. Uponreceiving the signal indicating the reception of the request foraccessing the design, the obfuscator tool 182 accesses an entry, such asthe first entry, to determine whether the design is designated asprivate or public.

In the embodiment, the obfuscated design is sent, by the obfuscator tool182, via the computer network 110 to the user computing device 2operated by the user 2 for display on the user computing device 2 viathe user account 2. For example, the obfuscator tool 182 packetizes theobfuscated design by applying the communication protocol to generatepackets, and sends the packets via the computer network 110 and the useraccount 2 to the user computing device 2. In addition to sending theobfuscated design to the user computing device 2 via the computernetwork 110, the management server 152 sends a data sheet including aspecification for generating the design 1 via the computer network 110to the user computing device 2. The obfuscator tool 182 accesses thesecond entry when the requester 1 indicates via the requester account 1to access the design 1 and obfuscates one or more portions of the design1 to generate the obfuscated design, and sends the obfuscated design viathe computer network 110 to the requester computing device 1 for displayon the requester computing device 1. In addition to sending the design 1to the user computing device 1 via the computer network 110, themanagement server 152 sends a data sheet including a specification forgenerating the design 1 via the computer network 110 to the requestercomputing device 1. The obfuscator tool 182 further accesses the thirdentry when the user 2 indicates via the user account 2 to access thedesign 2 and deobfuscates, such as removes an opaque portion, or doesnot obfuscate one or more portions of the design 2 and sends the design2 via the computer network 110 to the computing device 2 operated by theuser 2 for display. In addition to sending the design 2 to the usercomputing device 2 via the computer network 110, the management server152 sends a data sheet including a specification for generating thedesign 2 via the computer network 110 to the user computing device 2.

The reward generator tool 316 generates a reward, such as a monetaryamount or the royalty, to a winner, e.g., a designer, etc., of a designin a competition. In an embodiment, the reward generator tool 316 isconnected to the credit and debit server system via the computer network110. For example, when the requester 1 operates the requester computingdevice 1 to send a request via the requester account 1 for a circuitdesign to the online design engineering system 102, and the user 1 winsthe competition among the users 1-N, the reward generator tool 316provides the reward to the credit and debit server system, and thecredit and debit server system debits an amount of the reward from adeposit account of the requester 1 and credits the amount to a depositaccount of the user 1.

The competition is generated by the design competition generator tool310 and is posted within the online design engineering system 102 foraccess by the computing devices 1 through N. For example, upon receivingthe data sheet including the specification for the electrical circuitfrom the requester 1 by the requester account 1, the design competitiongenerator tool 310 sends to the requester account 1 via the computernetwork 110 a request regarding whether the requester 1 wishes togenerate a competition for a design of the electrical circuit. Uponreceiving an indication via the requester computing device 1 and therequester account 1 for the generation of the competition, thecompetition generator tool 310 posts an indication of the competitionalong with the data sheet including the specification to the useraccounts 1 through N. For example, the competition generator tool 310provides, via the computer network 110 and the user accounts 1 throughN, to the user computing devices 1 through N a data sheet for which adesign is to be generated with the indication of the competition forgenerating the design. Moreover, the competition generator tool 310provides, via the computer network 110 and the user accounts 1 throughN, to the user computing devices 1 through N a competition entry option,such as a competition entry button. Upon viewing a display of thecompetition on display devices of the user computer devices 1 through N,one or more of the users 1 through N use respective user computingdevices 1 and select via the corresponding user accounts 1 through N thecompetition entry option. Upon receiving the selections of thecompetition entry option via the corresponding user accounts 1 through Nand the computer network 110, the competition generator tool 310 storesthe selections in the searchable storage 152 and associates theselections with the user accounts 1 through N that are accessed toprovide the selections.

The data sheet builder tool 318 generates a data sheet that includesfields for receiving a specification of the electrical circuit. Forexample, upon receiving an indicator from the requester account 1 foraccess to the data sheet, the data sheet builder tool 318 accesses thetemplate database of the searchable storage 162 to provide the datasheet to the requestor account 1. For example, the data sheet buildertool 318 reads the data sheet from the template database and applies thecommunication protocol to generate packets from the data sheet, andsends the packets via the computer network 110 and the requester account1 to the requester computing device 1. In an embodiment, the data sheetincludes results of a simulation of a design, or results of a test of aprototype incorporating the design. In one embodiment, the data sheet isa web-driven data sheet, which is accessed via the website that ismanaged by the design engineering entity.

The specification completeness checker tool 302 determines whether aspecification within a data sheet that is received from the requester 1via the requester account 1 and the computer network 110 is complete.For example, for a type of a design, e.g., a design of a buffer, adesign of an adder, a design of a multiplier, etc., the specificationcompleteness checker tool 302 checks whether all parameters of thespecification to generate the design are received in the data sheet.Upon determining that all the parameters are not received, thespecification completeness checker tool 302 generates a notification.The specification completeness checker tool 302 sends the notificationvia the computer network 110 and the requester account 1 to therequester computing device 1 indicating the requester 1 that thespecification is incomplete. The requester 1 uses the requestercomputing device 1 to provide the remaining parameters within thespecification of the data sheet and sends the data sheet via thecomputer network 110 and the requester account 1 to the specificationcompleteness checker tool 302.

The specification compliance checker tool 320 determines whether aspecification received from the requester complies with specificationcompliance rules, which are stored in a specification compliancedatabase of the searchable storage 162. Examples of the specificationcompliance rules include whether a parameter provided in thespecification is within a predetermined range, whether a distanceprovided in the specification between two adjacent design components iswithin a preset limit, a number of pin ins of a design, a number of pinouts of the design, and whether a distance provided in the specificationbetween two adjacent planes is within a predetermined limit. It shouldbe noted that in some embodiments, pin ins and input pins are usedinterchangeably herein. Moreover, pin outs and output pins are usedinterchangeably herein.

The design searcher tool 322 searches for designs within the designdatabase 160 of FIG. 2. For example, the requester computing device 1sends via the requestor account 1 and the design search field or theuser computing device 2 sends via the user account 2 and the designsearch field a request to search for a design to the online designsearcher tool 322 via the computer network 110. The request includes thename of the design, such as, an encoder or an multiplexer or anamplifier or a voltage regulator. Based upon the request, the designsearcher tool 322 searches for a design within the design database 160whose name matches a name of the design within the request. When thereis a match between the name of the design within the design database 160and the design within the request, the design searcher tool 322, sends arequest to the obfuscator tool 182. The obfuscator tool 182 access thepublic-private indicator database 220 to determine whether the requestoraccount 1 or the user account 2 has permission from the user 1 thatgenerated the design to access the design. Upon determining that therequestor account 1 or the user account 2 does not have the permission,the obfuscator tool 182 obfuscates one or more portions of the design togenerate an obfuscated design and sends the obfuscated design via thecomputer network 110 to the user computing device 2 or the requestorcomputing device 1 for display of the obfuscated design. On the otherhand, upon determining that the requestor account 1 or the user account2 has the permission, the obfuscator tool 182 deobfuscates or does notobfuscate the design and sends the design via the computer network 110to the user computing device 2 or the requestor computing device 1 fordisplay of the design via the user account 2 or the requester account 1.

The requester 1 via the requester account 1 sends a request forgenerating a derivative of the first integrated circuit chip design.Upon receiving the request, the derivative generator tool 324 generatesa derivative of the first integrated circuit chip design. For example,the derivative generator tool 324 couples an integration circuit design,such as a glue logic design, with a first circuit design to create afirst integrated circuit chip design and couples the integration circuitdesign with a second circuit design, which is a derivative of the firstcircuit design, to create a second integrated circuit chip design. Theintegration circuit design is stored in the searchable storage 162 andis accessed, such as read, by the derivative generator tool 324 from thesearchable storage 162. In one embodiment, the derivative generator tool324 recommends a derivative of a circuit design and sends therecommendation via the computer network 110 and the requester account 1to the requester computing device 1.

In an embodiment, the derivative includes a change in one or morecomponents of the first circuit design to generate the second circuitdesign with the changed components that perform the same functions asthat performed by the one or more components. For example, multiplelogic gates of the first circuit design are replaced by gates of a lowernumber in the second circuit design. For example, multiple transistorsof the first circuit design are replaced by transistors of a lowernumber in the second circuit design. In one embodiment, the derivativeallows for an increase in efficiency, features or a reduction in cost orspace on an integrated circuit.

The prototype tester and test report generator tool 306 generates a testreport that includes results of testing a prototype of the electricalcircuit. In an embodiment, the prototype tester and test reportgenerator tool 306 includes instructions as to how to connect theprototype to a computing device for testing the prototype.

The use counter tool 312 keeps a record of a number of uses of a design.For example, a number of times for which a design is used in a prototypeof an integrated circuit chip and/or a number of times the circuitdesign is used by one or more of the users 1 through N is determined bythe use counter tool 312. To illustrate, a number of integrated circuitsin which a design is to be implemented are provided from a fabricationcomputing device operated by a fabrication entity. The fabricationentity uses the fabrication computing device to access a fabricationentity account 1, described below, to provide the number of integratedcircuits via the computer network 110 to the use counter tool 312. Asanother example, the use counter tool 312 counts a number of tests thata design has passed. To illustrate, the use counter tool 312 requeststhe data sheet builder tool 318 to provide a total of a number of timesfor which a circuit design generated based on a specification passes asimulation test, a layout design generated based on the specificationpasses a simulation test, and a prototype generated based on thespecification passes a test. The data sheet builder tool 318 generatesthe total and sends the total to the use counter tool 312. The number ofuses is used by the online design engineering system 102 for one or morepurposes, e.g., calculate a royalty, calculate a monetary amount toprovide to a designer of a design, calculate a design rating of thedesign or a designer rating of the designer, etc.

The design simulation report generator tool 184 generates a designsimulation report that includes results of a simulation of a schematicof a circuit design and/or results of a simulation of a layout design.For example, the design simulation report generator tool 184 generates adesign simulation report that indicates a result of the local circuitdesign test performed by the user 1 via the user account 1, theapplication of the circuit design verification tool 188 by the automaticcertification server 112, and/or the application of the local circuitverification tool used by one or more of the users 2-N of the community.As another example, the design simulation report generator tool 184generates a design simulation report that indicates a result of thelocal layout design test performed by the user 1 via the user account 1,the application of the layout design verification tool 190 by theautomatic certification server 112, and/or the application of the locallayout verification tool used by one or more of the users 2-N of thecommunity.

The design competition generator tool 310 receives a request for acircuit design competition from the requester 1 via the requestoraccount 1 and the computer network 110, and posts a competition forgenerating a circuit design based on the request. For example, thedesign competition generator tool 310 receives a specification for acircuit design from the requester, and posts the specification andterms, e.g., time limit of the competition in which the circuit designis to be submitted to the online design engineering system 102, rewardfor winning the competition, etc., of the competition. The designersthat control the computing devices 1 through N receive the specificationand the terms of the competition from the design competition generatortool 310 via the computer network 110 and compete by generating designsaccording to the specification. The generated designs are submitted bythe designers via the computing devices 1 through N and the computernetwork 110 to the online design engineering system 102. The onlinedesign engineering system 102 evaluates the circuit designs based on thespecification and terms of the competition to determine one or morewinners of the competition. Results, such as, name of the one or morewinners and one or more of the user accounts 1 through N, are posted bythe online design engineering system 102 within the one or more of theuser accounts 1 through N for access by one or more of the correspondingusers 1 through N via the computer network 110. Moreover, the results ofthe competition are provided to the requester computing device 1 via thecomputer network 110 so that the requester entity 1 can provide anaward, such as a reward, to the one or more winners via the computernetwork 110, the online design engineering system 102, and/or the creditand debit server system. For example, a number of points are awarded tothe one or more winners via the online design engineering system 102,and/or cash amounts are awarded to the one or more winners via thecredit and debit server system, etc.

The designer rating generator tool 326 generates a rating of thedesigner of the circuit design. For example, a designer who created acircuit design is rated on a scale of 1 to 10 based on a number of timesthe circuit design is used in one or more integrated circuits, and/or anumber of times the circuit design is accessed via one or more of theuser accounts 1 through N that have not been used to create the circuitdesign, and/or a number of times the circuit design is accessed by therequester computing device, and/or comments posted by one or more of theother users 1 through N regarding the designer to the comments database,etc.

The design rating generator tool 192 generates a rating of a designbased on a number of uses of the design, and posts the rating to one ormore servers that are controlled, e.g., leased by, owned by, etc., bythe online design engineering system 102 for access by the computingdevices 1 through N, the requester computing device, and/or the one ormore servers controlled by the one or more fabrication entities. In anembodiment, a design is rated based on a number of times the design isused in one or more integrated circuits, and/or a number of commentsmade on the design, and/or a number of times for which the design passesone or more tests, and/or a number of times the design is accessed viaone or more of the user accounts 1 through N that have not been used tocreate the circuit design, and/or a number of times the design isaccessed by the requester computing device, etc. To illustrate, when afirst design passes a higher number of tests compared to a seconddesign, the first design is assigned a higher rating by the designrating generator tool 192 compared to the second design.

The design project searcher tool 328 searches for a design project thatis posted by the requester computing device 1 onto the online designengineering system 102 via the computer network 110. For example, theuser 2 uses the computing device 2 to provide a search query for aproject for generating a circuit design. The search query includes aname, such as an analog-to-digital converter, a digital-to-analogconverter, an adder, or a multiplexer, of an integrated circuit to bedesigned. As an example, the name of an integrated circuit identifiesfunctionality of the integrated circuit. The search query is sent viathe computer network 110 to the online design engineering system 102.The design project searcher tool 328 searches the specification database160 that is connected to the online design engineering system 102 forthe project, such as a specification, based on the name of theintegrated circuit. The project is retrieved from a project database,such as the specification database 104, and provided via the computernetwork 110 to the computing device 2. For example, a data sheetincluding a specification for generating a circuit design is providedvia the computer network 110 to the computing device 2. The projectdatabase is stored within the searchable storage 162. For example, theproject database includes specifications for generating designs. Inaddition, in this example, the project database includes an indicationfor each specification whether one or more designs are generated basedon the specification. When one or more designs are generated based onthe specification and the designs pass simulation tests, describedherein, and/or one or more integrated circuit chips are fabricatedhaving the one or more designs and the one or more integrated circuitchips pass one or more validation tests, described herein, the projectis marked by the management server 152 as completed within the projectdatabase. Otherwise, the project is marked by the management server 152as being incomplete within the project database. Once a project ismarked as complete. The user 2 can then start generating a design basedon the specification within the data sheet.

It should be noted that in an embodiment, any output, e.g., royaltyamounts, obfuscated circuit design, award for a design, a data sheet,results of whether a data sheet is complete, results of whether aspecification is compliant, a schematic of the design, a layout of thedesign, a test report of testing a prototype generated based on thedesign, a simulation result of running a simulation on a design, aresult of the competition, a rating of a designer, a rating of thedesign, a design project, etc., generated by any of the tools of theonline design engineering system 102 are provided via the computernetwork 110 to the requester computing device or the one of thecomputing devices 1 through N that have a permission to receive theoutput.

In one embodiment, any of the tools, described herein, of the onlinedesign engineering system 102 is coupled to the searchable storage 162.For example, the design tools 158 are coupled to the searchable storage162 via a communication medium, such as a serial transfer communicationmedium, a parallel transfer communication medium, or a universal serialbus communication medium, or a combination thereof. As another example,any of the tools, described herein, are coupled to the searchablestorage 162 via the computer network 110.

FIG. 4A is a diagram of an embodiment of a system 400 to illustrateobfuscation of a design. The requester 1 requests the management server152 via the requestor computing device 1 and the computer network 110for a design based on the specification S1. For example, the requester 1requests the management server 152 to provide a circuit design based onthe specification S1. The management server 152 posts the request to theuser accounts 1 through N. The user 1 accepts the request via the useraccount 1 for generating the circuit design, and generates the schematic1830. The user 1 uses the computing device 1 to access the circuitdesign tool 164 from the circuit design tool database 206 (FIG. 2) togenerate the schematic 1830 of the circuit design. The circuit designtool 164 is executed to generate graphics representing circuit designcomponents, such as, transistors, logic gates, and connections betweenthe transistors connections between the logic gates. Other examples ofthe circuit design tool 164 includes a computer software program that isaccessed to draw the schematic 1830 of the circuit design. The schematic1830 is drawn by the user 1 by providing one or more inputs via theinput device of the computing device 1. The schematic 1830 is providedfrom the user computing device 1 to the management server 152 via theuser account 1 and the computer network 110.

Upon generating the schematic 1830 of the circuit design, the user 1accesses, via the computing device 1 and the computer network 110, fromthe layout design tool database 208, the layout design tool 166 thatincludes representations of IP blocks for generating the layout design127 based on the schematic 1830 of the circuit design. For example, theonline design engineering system 102 receives the schematic 1830 of thecircuit design from the computing device 1 via the computer network 110and an indication, e.g., a selection made by the user 1 via an inputdevice connected to the computing device 1, etc., from the computingdevice 1 that a layout is to be generated from the schematic. Uponreceiving the indication, the online design engineering system 102allows the user 1 access via the computing device 1 to the layout designtool 166 from the layout design tool database 208 to generate the layoutdesign 127 based on the schematic 1830.

In one embodiment, one or more fabrication entities, such as thefabrication entities 1 and 2, access, via the website, corresponding oneor more fabrication entity accounts to receive access to a foundryinterface tool 406. The one or more fabrication entities operate thecorresponding one or more fabrication computing devices to upload thelayout design tool database 208 to the searchable storage 162 via thefoundry interface tool 406. Examples of the foundry interface tool 406include a combination of hardware, such as processors, and computerprograms that allow communication between a fabrication computing deviceand the online design engineering system 102 to send the layout designtool database 208 via the computer network 110 from the fabricationcomputing device to the management server 152 for storing the layoutdesign tool database 208 in the searchable storage 162.

The schematic 1830 is stored in a circuit design file by the managementserver 152 and the layout design 127 is stored in a layout design fileby the management server 152. The circuit design file and the layoutdesign file are stored in the design database 160 by the managementserver 152. After the circuit design file and the layout design file arestored in the design database 160, the design serving manager tool 402of the online design engineering system 102 accesses, such as reads, thecircuit design file and the layout design file from the design database160 and provides the circuit design file and the layout design file viathe requestor account 1 of the requester 1 and the computer network 110to the requester computing device 1. For example, the design servingmanager tool 402 applies the communication protocol to packetize thecircuit design file and the layout design file to generate packets, andsends the packets via the computer network 110 to the requestercomputing device 1.

In an embodiment, when one of the users 2-N requests the circuit designfile and the layout design file and the user 1 has not providedpermission via the user account 1 to access the circuit design andlayout design files, the obfuscator tool 182 obfuscates one or moreportions of the schematic 1830 of the circuit design to generate anobfuscated circuit design. For example, one or more components and/orone or more connections between two adjacent components of the schematic1830 are covered by opaque blocks or opaque portions. Moreover, theobfuscator tool 182 obfuscates the layout design 127 to generate anobfuscated layout design. In an embodiment, the layout design 127 isobfuscated in that an arrangement of IP layers, such as the tiles, ofthe layout design 127 and/or connections between the IP blocks and/orthe IP layers are obfuscated from being displayed via one or more of theuser accounts 2-N on display devices of the corresponding computingdevice 2-N. For example, one or more overlay layers are generated andplaced by the obfuscator tool 182 on top of the IP layers and/or areplaced on top of the arrangement of the IP layers and/or on top of theconnections between the IP layers. The schematic 1830 and the layoutdesign 127 are obfuscated before being presented to the users 2 throughN. In an embodiment in which one or more of the other users 2 through Nhas permission from the online design engineering system 102 to view theschematic 1830 and the layout design 127, the schematic 1830 and thelayout design 127 are not obfuscated or deobfuscated by the obfuscatortool 182 before presenting the schematic 1830 and the layout design 127via one of the user accounts 2 through N on a display device of one ofthe user computing devices 2 through N.

In an embodiment, the circuit design file and the layout design file areaccessed by the design serving manager tool 402 to provide to a shuttlemanager tool 404 of the online design engineering system 102. Theshuttle manager tool 404 determines whether a pre-determined number ofdesigns, such as layout designs or circuit designs and correspondinglayout designs, are received from one or more of the user accounts 1through N via the computer network 110 for implementing the designs onthe shuttle, e.g., a wafer, etc. The implementation is performed by theone or more fabrication entities. Upon determining that thepre-determined number of designs are received from one or more of theuser accounts 1 through N, the shuttle manager tool 404 sends a requestvia the foundry interface tool 406 and the computer network 110 to thefabrication computing devices 1 and 2 of the one or more foundryentities for implementing the pre-determined number of designs on theshuttle to manufacture prototypes of SoCs based on the designs. Forexample, the shuttle manager tool 404 sends the request via the foundryinterface tool 406, and the fabrication entity account 1 to thefabrication computing device 1 that is operated by a first foundryentity. As another example, the shuttle manager tool 404 sends therequest via the foundry interface tool 406, and the fabrication entityaccount 2 to the fabrication computing device 2 that is operated by asecond foundry entity.

In one embodiment, the shuttle manager tool 404 sends the request forthe prototypes when an indication is received from requesters viacorresponding requester accounts for fabrication of the prototype. Forexample, the shuttle manager tool 404 accesses a data sheet to determinewhether the data sheet includes a request from the requester 1 via therequester account 1 for generation of a prototype based on parameters ofa design described in the data sheet. As another example, the shuttlemanager tool 404 accesses the requester account 1 to determine whether aprototype generation option, such as a prototype generation button, isselected by the requester 1 via the requester account 1. The requester 1uses the requester computing device 1 to access the requester account 1to further select the prototype generation option. A reception ofselection of the prototype generation option indicates to the shuttlemanager tool 404 that the requester 1 wishes to generate a prototype ofan integrated circuit chip.

A fabrication entity 1 uses the fabrication computing device 1 to accessthe fabrication entity account 1 to receive the request for fabricationof prototypes of SoCs based on the designs. For example, the fabricationentity 1 uses the fabrication computing device 1 to access the websitethat is controlled by the design engineering entity, and provides logininformation, such as an e-mail address or password or a combinationthereof, to access the fabrication entity account 1 assigned to thefabrication entity by the online design engineering system 102. Theauthenticator tool 332 of the online design engineering system 102determines whether the login information received from the fabricationcomputing device 1 via the computer network 110 is authentic, such asmatches data that is stored in the login database of the online designengineering system 102. Upon determining that the login informationreceived from the fabrication computing device 1 is authentic, thefabrication entity 1 that is assigned the login information is allowedby the authenticator tool 332 to access the fabrication entityaccount 1. On the other hand, upon determining that the logininformation received from the fabrication computing device 1 is notauthentic, the fabrication entity 1 is not allowed access by theauthenticator tool 332 to access the fabrication entity account 1.

FIG. 4B-1 is a diagram to illustrate obfuscation of the schematic 1830and of the layout design 127. The user 1 accesses circuit design tool164 from the circuit design tool database 206 via the computing device1, the user account 1, and the computer network 110 to generate a subcircuit design A (SCA), a sub circuit design B (SCB), and a sub circuitdesign C (SCC). A sub circuit design is one or more components of theelectrical circuit. The sub circuit designs A, B, and C are connected toeach other via a number of connections, e.g., wires, links, etc., togenerate the schematic 1830 of a design A. For example, an output of thesub circuit design A is connected to an input of a first instance of thesub circuit design B and an output of the first instance of the subcircuit design B is connected to an input a first instance of the subcircuit design C. Moreover, an output of the a second instance of subcircuit design C is connected to an input of a second instance of thesub circuit design B and an output of the second instance of the subcircuit design B is connected to an input of the first instance of thesub circuit design B. An instance is a component. For example, twoinstances of the same sub circuit design are the same two components,such as two N-type transistors, two OR logic gates, or two AND logicgates.

In an embodiment, a connection between the output of the second instanceof the sub circuit design C and the input of the second instance of thesub circuit design B is obfuscated by the obfuscator tool 182 byapplying an obfuscation connection layer c, e.g., an opaque block, anopaque shape, etc. Moreover, a connection between the output of the subcircuit design A and the input of the first instance of the sub circuitdesign B is obfuscated by the obfuscator tool 182 by applying anobfuscation connection layer a. Also, a connection between the output ofthe first instance of the sub circuit design B and the input of thefirst instance of the sub circuit design C is obfuscated by theobfuscator tool 182 by applying an obfuscation connection layer b.

It should be noted that in one embodiment, a connection between theoutput of the second instance of the sub circuit design B and the inputof the first instance of the sub circuit design B is not obfuscated bythe obfuscator tool 182 by applying an obfuscation connection layer whenthe connection is known, according to design rules stored in the circuitdesign tool database 206, to people having ordinary skill in the art ofcircuit design. In one embodiment, a connection between the output ofthe second instance of the sub circuit design B and the input of thefirst instance of the sub circuit design B is obfuscated by theobfuscator tool 182 by applying an obfuscation connection layer.

In an embodiment, instead of or in addition to placing the obfuscationconnection layers on the connections of the design A, an obfuscationlayer, such as an opaque portion or an opaque block, that covers theentire design A except for one or more pin inputs and/or one or more pinoutputs of the design A is generated and placed by the obfuscator tool182 of the online design engineering system 102 on the design A. Theplacement of the obfuscation layer covers, such as hides or rendersinvisible or renders as a black box, the sub circuit designs A, B, and Cand the connections between the sub circuit designs A, B, and C. Wheneither a connection between two adjacent sub circuits or a subcircuit ofthe schematic 1830 or the schematic 1830 except for one or more pininputs and/or one or more pin outputs of the design A is obfuscated, anobfuscated portion a is generated by the obfuscator tool 182.

The user 1 access via the user account 1 and the user computing device 1the layout design tool 166 from the layout design tool database 208 ofthe online design engineering system 102 to generate the layout design127, such as a physical layout, etc., of the design A based on theschematic 1830. For example, the physical layout of the design Aincludes cells C1, C2, C3, C4, C5, C6, C7, C8, and C9, which arearranged and connected, e.g., placed and routed, etc., in a mannerillustrated in FIG. 4B-1. The arrangement and connection of the cells iscovered by the obfuscator tool 182 of the online design engineeringsystem 102 with an obfuscation layout, such as an opaque layer or anopaque portion or an opaque shape, except for one or more pin inputsand/or one or more pin outputs of the physical layout to hide thearrangement and connection from one or more of the user accounts 2through N and/or the requestor account 1 of the requester 1 that doesnot have permission from the user 1 via the user account 1 fordisplaying the arrangement and connection of the cells. In anembodiment, each of the cells C1, C2, C3, C4, C5, C6, C7, C8, and C9 iscovered by the obfuscator tool 182 with an obfuscation layer and/or aconnection between any two adjacent ones of the cells is covered by theobfuscator tool 182 with an obfuscation layer instead of the obfuscationlayer that covers the entire arrangement and connection of all thecells. When either a connection between two adjacent cells or a cell ofthe layout design 127 or the entire layout design 127 except for one ormore pin inputs and/or one or more pin outputs of the design A isobfuscated, an obfuscated portion b is generated by the obfuscator tool182.

In one embodiment, when a test, such as a simulation test or averification test, is executed on an obfuscated connection or anobfuscated portion, any values that are output at the obfuscatedconnection or the obfuscated portion are also obfuscated by theobfuscator tool 182. Examples of the obfuscated portion includes anobfuscated intermediate node, such as a component or a cell, between apin in and a pin out of a block. The obfuscated intermediate node is anoutput of a component, such as a gate or a transistor or a cell, of adesign. The values output are obfuscated and stored within a data sheet.The verification test is executed by the local test bench tool 165, orby the circuit design verification tool 188, or by the community, or bythe local layout verification tool 167, or by the layout designverification tool 190 of FIG. 1F. For example, when an account does nothave access to all portions of a design but has access to an obfuscateddesign, the obfuscator tool 182 obfuscates one or more portions of thedata sheet having the values before the data sheet is accessed via theaccount.

FIG. 4B-2 is a diagram of an embodiment of a system 450 to illustratedifferent integrated circuit chips on a wafer, such as a semiconductorsubstrate. The derivative generator tool 324 of the online designengineering system 102 provides an option via the computer network 110and the user account 1 to the computing device 1 to integrate the designA within an integrated circuit chip design 1. Upon receiving a selectionof the option via the input device connected to the computing device 1from the user account 1, the derivative generator tool 324 connects thedesign A to an integration circuit design 452, which includes one ormore pre-determined designs, of the integrated circuit chip design 1.For example, the integration circuit design 452 includes one or morecells that couple to one or more cells of the design A and furtherinclude pin inputs and pin outputs of the integrated circuit chipdesign 1. As another example, one or more cells on each plane of theintegration circuit design 452 couple to one or more cells on acorresponding plane of the design A. For example, the integrationcircuit design 452 has planes 1 and 2 and the plane 1 is below the plane2. Similarly, the design A has planes 1 and 2 and the plane 1 is belowthe plane 2. One or more cells of the plane 1 of the integration circuitdesign 452 couple to one or more cells of the of the plane 1 of thedesign A. Moreover, one or more cells of the plane 2 of the integrationcircuit design 452 couple to one or more cells of the of the plane 2 ofthe design A.

In an embodiment, the derivative generator tool 324 of the online designengineering system 102 generates a derivative, e.g., a design B, etc.,of the design A. For example, there is a different type of gatesubstituted by online design engineering system 102 in the design Bcompared to that of the design A but the remaining structure of thedesign B is the same as that of the design A. As another example, thereis a change in a predetermined number of connections between cells ofthe design A to generate the design B. The change is made by the onlinedesign engineering system 102. As yet another example, there is asubstitution of one cell with another cell of the design A to generatethe design B. The substitution is made by the online derivativegenerator tool 324. In an embodiment, the derivative is generated uponreceiving a selection from the user 1 via the input device connected tothe user computing device 1, the user account 1, and the computernetwork 110. In one embodiment, the design B is generated by the user 1or another one of the users 2 through N by applying the layout designtool 166 to the design A.

Moreover, upon receiving a selection from the user 1 via the inputdevice connected to the user computing device 1, the user account 1, andthe computer network 110 indicating that the design B is to be connectedto the integration circuit design 452, the derivative generator tool 324connects the design B to the integration circuit design 452 to generatean integrated circuit chip design 2.

The integrated circuit chip designs 1 and 2 are provided by themanagement server 152 from the user account 1 to the shuttle managertool 404 for reserving spots on the wafer for fabricating prototypes,e.g., an integrated circuit chip 1 (ICC1) and an integrated circuit chip2 (ICC2), etc., of the integrated circuit chip designs 1 and 2.Similarly, in an embodiment, a prototype, which is an integrated circuitchip 3 (ICC3), is generated. The shuttle manager tool 404 receives arequest from the user computing device 1 via the computer network 110 tobe sent to the fabrication entity 1 for fabricating the prototypes. Therequest identifies, via names or alphanumeric characters, design filesin which the integrated circuit chip designs 1 and 2 are stored. Theshuttle manager tool 404 accesses the design files from the designdatabase 160 based on the identities of the design files, and sends thedesign files with the request to the fabrication entities 1 and 2 viathe fabrication entity accounts 1 and 2 to the corresponding fabricationcomputing devices 1 and 2. For example, the shuttle manager tool 404receives the request from the user computing device 1 via the computernetwork 110 to be sent to the fabrication entity 1 for fabricating theprototypes. The shuttle manager tool 404 sends the request with thedesign files in which the integrated circuit chip designs 1 and 2 arestored via the fabrication entity account 1 to the fabrication computingdevice 1. Similarly, the shuttle manager tool 404 sends the request withthe design files in which the integrated circuit chip designs 1 and 2are stored to another foundry entity 2 via the fabrication entityaccount 2 to the fabrication computing device 2. The foundry entity 1accepts the request for fabricating the prototypes ICC1, ICC2, and ICC3on the wafer via the fabrication entity account 1 and sends theacceptance via the fabrication entity account 1 and the computer network110 to the user account 1. In one embodiment, the request for generatinga prototype based on the integrated circuit chip design 2 is received bythe shuttle manager tool 404 from the user computing device 2 via theuser account 2 and the computer network 110 instead of from the usercomputing device 1 via the user account 1 and the computer network 110.

The wafer is processed, e.g., etched, cleaned, deposited on,photomasked, sputtered, doped, etc., by the fabrication entity 1 byusing a processing tool, e.g., a plasma chamber, etc., to fabricate andconnect circuit components on the wafer to generate the integratedcircuit chips ICC1, ICC2, and ICC3. The integrated circuit chips ICC1,ICC2, and ICC3 are removed by the foundry entity 1 from the wafer bycutting.

In an embodiment, the integrated circuit chip ICC1 is tested by thefabrication entity 1 by connecting the integrated circuit chip ICC1 to aprinted circuit board and connecting the printed circuit board to thefabrication computing device 1 via one or more connections, e.g., serialconnection, parallel connection, USB connection, one or more wires, acable, etc. In one embodiment, the integrated circuit chip ICC1 isprovided, such as mailed, to the user 1 and the user 1 uses the usercomputing device 1 to access the prototype tester and test reportgenerator tool 306 (FIG. 3) to test the integrated circuit chip ICC1.For example, the prototype tester and test report generator tool 306 isa computer program executed by a processor of the management server 152to provide one or more input values to the integrated circuit chip 1 andreceive one or more output values from the integrated circuit chip 1.Based on the one or more output values and pre-determined criteria forpassing a test, the prototype tester and test report generator tool 306determines whether the integrated circuit chip 1 passes or fails thetest. It should be noted that the prototype tester and test reportgenerator tool 306 is not downloaded to the user computing device 1. Forexample, the management server 152 receives a request from the useraccount 1 for a download of the prototype tester and test reportgenerator tool 306 and determines based on permissions associated withthe user account 1 whether the user account 1 has permission to downloadthe prototype tester and test report generator tool 306. Upondetermining that the user account 1 does not have the permission for thedownload, the management server 152 does not allow the download from theonline design engineering system 102 via the computer network 110 to theuser computing device 1. Similarly, the integrated circuit chips ICC2and ICC3 are tested.

In one embodiment, instead of the integration circuit design 452, anyother integration circuit design that is pre-stored in the searchablestorage 162 before the design A or design B is created is used to coupleto the design A or the design B. The other integration circuit design iscreated by a user or by the design engineering entity or is obtainedfrom another entity via the computer network 110.

FIG. 5A is a diagram of an embodiment of a system 500 to illustrate acompetition for generating a design. The system 500 includes therequester computing device 1, the user computing device 1, the usercomputing device N, and the online design engineering system 102. Therequester 1 uses the requester computing device 1 to send via therequester account 1 and the computer network 110 a request for a designto the online design engineering system 102. Upon receiving the requestfor the design, the design competition generator tool 310 (FIG. 3) ofthe online design engineering system 102 generates a competition for thedesign and posts the competition within the user accounts 1 through Nvia the computer network 110. For example, the competition is posted onthe website that is controlled by, e.g., leased by, owned by, etc., thedesign engineering entity that controls the online design engineeringsystem 102, and the posting of the competition on the website isaccessible via the user accounts 1 through N.

The users 1 through N access the user accounts 1 through N to view theposting of the competition displayed on the corresponding user computingdevices 1 through N. The users 1 through N enroll via corresponding useraccounts 1 through N in the competition and generate designs by applyingthe circuit design tool 164 and/or the layout design tool 164. The user1 uses the computing device 1 to send a design 1 via the user account 1and the computer network 110 to the management server 152 of the onlinedesign engineering system 102. Moreover, the user N uses the computingdevice N to send a design N via the computer network 110 to themanagement server 152 of the online design engineering system 102. Thedesign rating generator tool 192 (FIG. 3) of the online designengineering system 102 generates a rating, e.g., a ranking, etc., of thecircuit designs 1 and N based on predetermined rules. For example, whenthe design 1 is used for a greater number of times compared to thedesign N, the design 1 is ranked higher than the design N. The rating issent from the design rating generator tool 192 of the online designengineering system 102 via the computer network 110 and the requesteraccount 1 to the requester computing device 1. In an embodiment, therating of the designs 1 and N is posted within one or more of the useraccounts 1 through N accessible via the website. The requester 1 via therequester computing device 1 determines, based on the rating, whether toselect the circuit design 1 or N. For example, if the rating of thedesign 1 is greater than the rating of the design N, the requester 1 viathe requester computing device 1 and the requester account 1 selects thedesign 1. An indication of the selection of the design 1 is sent fromthe requester computing device 1 via the requester account 1 and thecomputer network 110 to the reward generator tool 316.

Upon receiving the indication of the selection of the design 1 via thecomputer network 110 from the requester computing device 1, the rewardgenerator tool 316 (FIG. 3) of the online design engineering system 102generates a reward for the design 1 and sends the reward via thecomputer network 110 to the user account 1 of the user 1, who won thecompetition. For example, the online design engineering system 102communicates with the credit and debit system to credit a predeterminedmonetary amount via the computer network 110 to a deposit account of theuser 1. It should be noted that in an embodiment, deposit accounts ofthe users 1 through N are connected via the computer network 110 to thecredit and debit system.

In one embodiment, an amount of the reward is received and stored withinthe searchable storage 162 by the reward generator tool 316. Forexample, the requester 1 operates the requester computing device 1 toprovide a dollar amount of the reward via the computer network 110 tothe reward generator tool 316 and the reward generator tool 316 storesthe dollar amount within the searchable storage 162 for later providingthe reward to the user account 1.

FIG. 5B is a diagram of an embodiment of a design challenge, which isposted within the user accounts 1 through N when the requester 1 postswithin the requester account 1 a request for a design. The requester 1logs into the requester account 1 to indicate to the management server152 the design challenge to fabricate a prototype of an embeddedultra-low power voltage reference. For example, the requester 1 operatesthe requester computing device 1 to submit via the requester account 1and the computer network 110 the parameters of a specification within adata sheet for generating the design challenge. The design challenge isa challenge for generating a design based on the specification.Moreover, the requester 1 also indicates, within the data sheet, a duedate for delivery of the prototype. The design competition generatortool 310 of the management server 152 receives the design challenge,embodied in the form of a data sheet, and posts the design challenge tothe user accounts 1 through N. For example, the design competitiongenerator tool 310 posts within the user accounts 1 through N the datasheet and a posting that a cash award will be provided to top threewinners. Moreover, the design competition generator tool 310 postswithin the user accounts 1 through N that all participants, such as theusers 1 through N, who accept the design challenge will retainintellectual property ownership of designs that they create via thecorresponding user accounts 1 through N. As an example, the data sheetbuilder tool 303 receives an acceptance of the design challenge by thecomputer network 110 and the user account 1 from the user computingdevice 1.

FIG. 6 is a diagram of an embodiment of a system 600 to illustrate aserial process by which a design of the electrical circuit is generated.The requester 1 submits a request for generation of a first design, suchas a design 1, of an integrated circuit to a foundry entity. A cost tothe requester 1 for submitting the request to the foundry entity is $z1.Moreover, a probability of success that the design of the integratedcircuit will be completed adherent to the requester-providedspecifications is β1%. Once the integrated circuit is delivered, asecond design, such as a design 2, of another integrated circuit isrequested by the requester 1. Similarly, request and completion ofintegrated circuits based on a third design and a fourth design, such asa design 3 and a design 4, are serial processes.

FIG. 7 is a diagram of an embodiment of a system 700 to illustrate aparallel process in which multiple designs of the electrical circuit aregenerated by the online design engineering system 102. For example, inthe same or less amount of time taken to perform the serial process, thefirst through fourth designs for fabricating a prototype of theelectrical circuit are generated. The requester 1 submits via therequester account 1 a request for generation of a design of anintegrated circuit to the online design engineering system 102. Theonline design engineering system 102 posts the request to the useraccounts 1 through N for generating the design and the request isaccessible within the user accounts 1 through N via the website. Theusers 1 through N apply the circuit design tool 164 and the layoutdesign tool 166 to generate the first through fourth designs of theintegrated circuit. The first through fourth designs are generated inthe parallel manner by the users 1 through 4 via corresponding useraccounts 1 through 4 in which a lesser amount of time is spent comparedto the serial process of FIG. 6. The design simulation report generatortool 184 (FIG. 3) of the online design engineering system 102 determinesthat the first and second designs are compliant to the specification ofthe design provided by the requester 1 via the requester account 1. Therequester 1 chooses via the requester account 1 one or more of the firstand second designs, which are compliant. The online design engineeringsystem 102 sends a request to the credit and debit server system tocredit a deposit account of the users 1 and 2 that generated the firstand second designs with payments of $x1 and $x2 respectively. A cost tothe requester 1 for submitting the request for the design to the onlinedesign engineering system 102 is $z2, which is lower than $z1. Moreover,a probability of success that the design of the integrated circuit willbe completed and adherent to the requester-provided specification isβ2%, which is greater than β1%.

FIG. 8 is a diagram of an embodiment to illustrate fabrication andtesting of a prototype of an integrated circuit. The user 1 via the usercomputing device 1 and the user account 1 accesses the layout designtool database 208 for accessing cells C2 and C4 from multiple cells C1through C4. The cells C2 and C4 are placed by the user 1 via the inputdevice of the user computing device 1 to create the layout design 127.The layout design tool database 208 stores rules regarding bonding wiresbetween different cells of the layout design 127. When the user 1 viathe user computing device 1 and the user account 1 bonds wires betweendifferent cells of the layout design 127, the rules regarding bondingare applied by the layout design tool 166. Examples of the rulesregarding bonding include an arrangement of bond pads on the layoutdesign 127, a minimum ratio of length to width of the layout design 127,and a length of each wire. Moreover, the layout design tool database 208stores rules regarding packaging of an integrated circuit having thelayout design 127. Examples of rules regarding packaging includedimensions of a package of an integrated circuit, a material of thepackage, a number of pins extending from the package, and a distancebetween two adjacent pins of the package.

The layout design verification tool 190 of FIG. 1F executes a modulartesting flow to test each cell of the layout design 127. Moreover, eachof the circuit design verification tool 188, the layout designverification tool 190 of FIG. 1F, and the prototype tester and testreport generator tool 306 of FIG. 3 include reusable test modules. Thereusable test modules are reusable for the same component of a design.For example, when the design 1 includes an OR gate and the design 2 alsoincludes an OR gate, the same test module of the circuit designverification tool 188 is executed to test both the OR gates. A module,as used herein, is a portion of a tool. In addition, common testfixtures, such as cables that connect a prototype of an integratedcircuit to a computing device for testing the prototype and emulatorsfor testing the prototype are provided by the design engineering entityto the users 1 through N for testing the prototype. For example, theuser 1 requests via the user account 1 the common test fixtures fortesting a prototype of an integrated circuit. Upon receiving therequest, the management server 152 identifies from the user account 1,address information, such as a residence address or a work address, ofthe user 1. The management server 152 sends the common test fixtures viaa mailing service to the residents of the work address of the user 1 fortesting the prototype of the integrated circuit.

The online design engineering system 102, described herein, provides aneasy design environment for chips, such as a prototype of an integratedcircuit. Moreover, the online design engineering system 102 provides amethod to quickly and economically validate circuit designs on silicon.For example, in two phases, designs with high predictability andcorrelation to silicon are provided, and labs, such as foundries,controlled by the online design engineering system 102 serve a physicalvalidation process in which the prototype tester and test reportgenerator tool 306 tests a prototype of an integrated circuit.Furthermore, a well verified library, e.g., the design database 160(FIG. 2), etc., of components, such as regulators and data converters,is provided by the online design engineering system 102. For example, anintegrated circuit chip design is stored in the design database 160, andaccessed later by the one of the users 1 through N via one of the useraccounts 1 through N assigned to the user, or by the requester 1 via therequester account 1, etc., from the design database 160. Any tiny glueor extra circuits, e.g., circuit designs or layout designs, areencapsulated in a new block and follow a certification and qualificationprocess, such as one managed by the design simulation report generatortool 184.

Also, a scalable backend process, which includes pre-designed andpre-qualified packages and bonding diagrams, an agile mark and assemblyprocess, and a dealing with high variation of part numbers andfunctional differences is provided by the online design engineeringsystem 102. Furthermore, a unified, standardized test method and flow,where each component or cell, such as a block, is tested using asimulation program, such as the circuit design verification tool 188 ofFIG. 1F or the layout design verification tool 190 of FIG. 1F, isscalable so that every integrated circuit chip design that uses the samecomponent uses the same simulation program without limitations fortesting. In an embodiment, analog test and diagnostic standards ofInstitute of Electrical and Electronics Engineers (IEEE) are accessed bythe online design engineering system 102 via the computer network 110from an IEEE database that is managed by IEEE, and are applied by thecircuit design verification tool 188, the layout design verificationtool 190, and the prototype tester and test report generator tool 306 ofFIG. 3 to test a design and a prototype of the design. For example, theIEEE standards are integrated and applied by the design simulationreport generator tool 184 (FIG. 3) and/or by the prototype tester andtest report generator tool 306 (FIG. 3), etc.

FIG. 9A is a diagram of an embodiment of an online design engineeringprocess 900 executed by the online design engineering system 102 togenerate the layout design 127. The requester 1 via the requestercomputing device 1 accesses the website that is controlled by the designengineering entity to access the requester account 1. Upon accessing therequester account 1, the requester 1 uses the input device of therequester computing device 1 to submit a request for a design of theelectrical circuit. For example, the requester 1 submits a specificationincluding parameters for generating a design of the electrical circuit.The management server 152 receives the request via the computer network110 and posts the request and the specification within the user accounts1 through N for engaging the community.

The users 1 through N use the corresponding, such as respective, usercomputing devices 1 through N to access the website to further accessthe corresponding user accounts 1 through N to view the request for thedesign and the specification. Upon viewing the requester and thespecification, the users 1 through N use the corresponding usercomputing devices 1 through N to access via the corresponding, such asrespective, user accounts 1 through N the circuit design tool 164 fromthe circuit design tool database 206 to create N circuit designs basedon the specification. Moreover, the users 1 through N use thecorresponding user computing devices 1 through N to access via thecorresponding user accounts 1 through N the local test bench tool 165from the searchable storage 162 to test the N circuit designs togenerate N simulation reports for the N circuit designs or to update adata sheet with results of the test. The data sheet builder tool 318updates the data sheet with results of the test. In one embodiment, theusers 1 through N use the corresponding user computing devices 1 throughN to indicate via the corresponding user accounts 1 through N to theautomatic certification server 112 to execute the circuit designverification tool 188. When the circuit design verification tool 188 isexecuted, the automatic certification server 112 generates the Nsimulation reports for the N circuit designs or the data sheet buildertool 318 updates a data sheet with results of the test.

Furthermore, the users 1 through N use the corresponding user computingdevices 1 through N to access via the corresponding user accounts 1through N the layout design tool 166 from the layout design tooldatabase 208 to create N layout designs based on the N circuit designs.Moreover, the users 1 through N use the corresponding user computingdevices 1 through N to access via the corresponding user accounts 1through N the local layout verification tool 167 from the searchablestorage 162 to test the N layout designs to generate N signoff reportsfor the N layout designs or to update a data sheet with results of thetest. The data sheet builder tool 318 updates the data sheet withresults of the test. In one embodiment, the users 1 through N use thecorresponding user computing devices 1 through N to indicate via thecorresponding user accounts 1 through N to the automatic certificationserver 112 to execute the layout design verification tool 190. When thelayout design verification tool 190 is executed, the automaticcertification server 112 generates the N signoff reports for the Nlayout designs or the data sheet builder tool 318 updates a data sheetwith results of the test.

In one embodiment, instead of or in addition to generating a simulationreport that includes a result of testing a circuit design, the result isintegrated within a data sheet that includes the specification.Moreover, instead of or in addition to generating a signoff report thatincludes a result of testing a layout design, the result is integratedwithin the data sheet that includes the specification.

FIG. 9B is a block diagram of an embodiment of a design engineeringprocess 920 for illustrating use of the online design engineering system102 in fabricating an integrated circuit chip. As shown in FIG. 9B, at astage 1 of the design engineering process 920, the requester 1 uses therequester computing device 1 and accesses the requester account 1 togenerate multiple requests for multiple integrated circuit chip designs.The requester 1 uses the input device of the requester computing device1 to provide parameters for generating multiple integrated circuitdesigns. The requests and the parameters are sent from the requestercomputing device 1 via the computer network 110 to the management server152 of the online design engineering system 102. Upon receiving therequest and the parameters, the management server 152 posts the requestsand the parameters to the user accounts 1 through N to engage thecommunity to generate specifications S1 through S3 based on theparameters. The users 1 through N access the respective user accounts 1through N via the respective computing devices 1 through N to generatethe specifications. For example, the users 1 through N add additionalparameters to generate the specifications S1 through S3.

The specification completeness checker tool 302 of the online designengineering system 102 determines whether the specifications S1 throughS3 are complete. For example, the specification completeness checkertool 302 determines whether all fields within data sheets having thespecifications S1 through S3 have values of the parameters. Furthermore,upon receiving the request and the specifications, the specificationcompliance checker tool 320 of the online design engineering system 102determines whether the specifications S1 through S3 comply with thespecification compliance rules such as whether values of the parametersare within corresponding predetermined ranges.

The specifications S1 through S3 are provided from the specificationcompliance checker tool 320 to the requester computing device 1 via thecomputer network 110 and the requester account 1 for selection of one ormore of the specifications S1 through S3. Upon receiving a selectionfrom the requester computing device 1 via the requester account 1 of thespecifications S1 and S2, at a stage 2 of the design engineering process920, the management server 152 engages the community by providing accessto the specifications S1 and S2 via the user accounts 1 through N to theuser computing devices 1 through N. The requester 1 via the requestercomputing device 1 and the requester account 1 indicates to themanagement server 152 of rejection of the specification S3. Themanagement server 152 indicates the rejection of the specification S3 toone of the user accounts 1 through N that is accessed by one of theusers 1 through N to generate the specification S3.

The user 1 generates circuit designs, sometimes referred to herein asfront-end designs, based on the specifications S1 and S2. Moreover,tests are run on the circuit designs to generate simulation reports. Forexample, the design simulation report generator tool 184 (FIG. 3) runsone or more simulations on circuit designs generated based on thespecifications S1 and S2. The design simulation report generator tool184 determines that the circuit design generated based on thespecification S1 passes the one or more simulations and the circuitdesign generated based on the specification S2 fails the one or moresimulations. This determination is a completion of a frontend process,in an embodiment, which occurs at a stage 3 of the design engineeringprocess 920. The management server 152 indicates the failure of the oneor more simulations to the user account 1 that is accessed by the user 1through N to generate the circuit design based on the specification S2.

The simulation reports include whether the circuit designs pass or failthe tests. The simulation reports are sent from the design simulationreport generator tool 184 of FIG. 3 via the computer network 110 and therequester account 1 to the requester computing device 1. The requester 1views the simulation reports displayed on the display device of therequester computing device 1 via the requester account 1 to select oneof the simulation reports for the circuit design generated based on thespecification S1.

The selection of the simulation report for the circuit design generatedbased on the specification S1 is sent from the requester computingdevice 1 via the requester account 1 and the computer network 110 to themanagement server 152. The management server 152 indicates the selectionto the user account 1 The user 1 views the selection posted to the useraccount 1 and generates a layout design, sometimes referred to herein asa backend design, for the circuit design generated based on thespecification S1. Furthermore, tests are run on the layout design togenerate a signoff report. For example, the design simulation reportgenerator tool 184 (FIG. 3) runs one or more simulations on layoutgenerated based on the specification S1. The design simulation reportgenerator tool 184 determines that the layout design generated based onthe specification S1 passes the one or more simulations. Thisdetermination is a completion of a frontend process, which occurs at astage 4 of the design engineering process 920. The signoff reportindicates that the layout design passes one or more tests.

The signoff report is sent from the design simulation report generatortool 184 of FIG. 3 via the computer network 110 and the requesteraccount 1 to the requester computing device 1. The requester 1 views thesignoff report displayed on the display device of the requestercomputing device 1 via the requester account 1. Upon viewing the signoffreport, the requester 1 uses the requester computing device 1 toindicate via the requester account 1 that a prototype is to be generatedbased on the signoff report for the layout design generated based on thespecification S1.

Upon receiving the indication that the prototype is to be generated viathe computer network 110 from the requester computing device 1, theshuttle manager tool 302 (FIG. 3) of the online design engineeringsystem 102 provides a file including the layout design for thespecification S1, a file including the circuit design for thespecification S1, and a file including the specification S1 via thecomputer network 110 and the fabrication entity account 1 to thefabrication computing device 1. The fabrication entity 1 fabricates aprototype of the integrated circuit chip from the layout design for thespecification S1, and sends the prototype via the mailing service to thedesign engineering entity. Upon receiving the prototype from thefoundry, the prototype tester and test report generator tool 306 (FIG.3) is executed under control of the design engineering entity to testthe prototype to validate or invalidate the prototype. The validation orinvalidation is done at a stage 5 of the design engineering process 920.Upon determining that the prototype is valid, the prototype is sent bythe design engineering entity via the mailing service to the fabricationentity 1 for fabricating integrated circuit chips based on theprototype. This occurs at a stage 6 of the design engineering process920.

In one embodiment, the derivative generator tool 324 (FIG. 3) of theonline design engineering system 102 integrates the layout design withthe integration circuit design 452 to generate an integrated circuitchip design. In an embodiment, the design simulation report generatortool 184 runs a simulation on the integrated circuit chip design todetermine whether the integrated circuit design passes or fails asimulation. Upon determining that the integrated circuit chip designpasses the simulation, in an embodiment, a backend process is completedat the stage 4 of the design engineering process 900. The shuttlemanager tool 302 (FIG. 3) of the online design engineering system 102provides a file including the integrated circuit chip design for thespecification S1, a file including the layout design for thespecification S1, a file including the circuit design for thespecification S1, and a file including the specification S1 via thecomputer network 110 and the fabrication entity account 1 to thefabrication computing device 1. The fabrication entity 1 fabricates aprototype of an integrated circuit chip from the integrated circuit chipdesign, and sends the prototype via the mailing service to the designengineering entity. Upon receiving the prototype from the foundry, theprototype tester and test report generator tool 306 (FIG. 3) is executedby the design engineering entity to test the prototype to validate orinvalidate the prototype. The validation or invalidation is done at thestage 5 of the design engineering process 920. Upon determining that theprototype is valid, the prototype is sent by the design engineeringentity via the mailing service to the fabrication entity 1 forfabricating integrated circuit chips based on the prototype. This occursat the stage 6 of the design engineering process 920.

It should be noted, that in an embodiment, at the end of the stage 2 ofthe design engineering process 920, a deposit account assigned to therequester 1 is debited by the credit and debit server system accordingto a predetermined percentage, e.g., 10%, etc., of a total cost, e.g.,100%, etc., of creating designs and fabricating integrated circuit chipsfrom a prototype of one of the designs. The predetermined percentage isgenerated by the royalty generator tool 304. The deposit account isdebited for crediting by the credit and debit server system thepredetermined percentage to a deposit account of one or more of theusers 1 through N that generated the specifications S1 through S3.Moreover, at the end of the stage 3 of the design engineering process920, a deposit account of the requester 1 is debited by the credit anddebit server system according to another predetermined percentage, e.g.,20%, etc., of the total cost. The other predetermined percentage isgenerated by the royalty generator tool 304. The deposit account isdebited for crediting by the credit and debit server system the otherpredetermined percentage to a deposit account of the one or more of theusers 1 through N that generated the circuit designs meeting thespecification S1 and S2 and passing one or more simulation tests. Also,at the end of the stage 4 of the design engineering process 920, adeposit account of the requester 1 is debited by the credit and debitserver system according to yet another predetermined percentage, e.g.,30%, etc., of the total cost. The yet another predetermined percentageis generated by the royalty generator tool 304. The deposit account isdebited for crediting by the credit and debit server system the yetother predetermined percentage to a deposit account of the user 1through N that generated the layout design meeting the specification S1and passing one or more simulation tests. At the end of the stage 5 ofthe design engineering process 900, a deposit account of the requester 1is debited by the credit and debit server system according to stillanother predetermined percentage, e.g., 30%, etc., of the total cost.The deposit account is debited for crediting by the credit and debitserver system the still other predetermined percentage to a depositaccount of the user 1 that generated the layout design meeting thespecification S1 and for which a prototype generated based on the layoutdesign is validated by one or more tests.

FIG. 9C is a block diagram of an embodiment of a design engineeringprocess 930 for illustrating use of the online design engineering system102 in fabricating an integrated circuit chip. As shown in FIG. 9C, at astage 1 of the design engineering process 930, the requester 1 uses therequester computing device 1 and accesses the requester account 1 togenerate multiple requests for multiple integrated circuit chip designs.The requester 1 uses the input device of the requester computing device1 to provide parameters for generating multiple integrated circuitdesigns. The requests and the parameters are sent from the requestercomputing device 1 via the computer network 110 to the management server152 of the online design engineering system 102. Upon receiving therequest and the parameters, the management server 152 posts the requestsand the parameters to the user accounts 1 through N to engage thecommunity to generate specifications S1 through S3 based on theparameters. The users 1 through N access the respective user accounts 1through N via the respective computing devices 1 through N to generatethe specifications. For example, the users 1 through N add additionalparameters to generate the specifications S1 through S3.

The specification completeness checker tool 302 of the online designengineering system 102 determines whether the specifications S1 throughS3 are complete. For example, the specification completeness checkertool 302 determines whether all fields within the specifications S1through S3 have values of the parameters. Furthermore, upon receivingthe request and the specifications, the specification compliance checkertool 320 of the online design engineering system 102 determines whetherthe specifications S1 through S3 comply with the specificationcompliance rules such as whether values of the parameters are withincorresponding predetermined ranges.

The specifications S1 through S3 are provided from the specificationcompliance checker tool 320 to the requester computing device 1 via thecomputer network 110 and the requester account 1 for selection of one ormore of the specifications S1 through S3. Upon receiving a selectionfrom the requester computing device 1 via the requester account 1 of thespecification S1, at a stage 2 of the design engineering process 930,the management server 152 engages the community by providing access tothe specification S1 via the user accounts 1 through N to the usercomputing devices 1 through N. The requester 1 via the requestercomputing device 1 and the requester account 1 indicates to themanagement server 152 of rejection of the specifications S2 and S3. Themanagement server 152 indicates the rejection of the specifications S2and S3 to one or more of the user accounts 1 through N that created thespecifications S2 and S3.

The user 1 generates via the user account 1 a circuit design schematicSCH1 based on the specification S1. Moreover, the user 2 generates viathe user account 2 a circuit design schematic SCH2 based on thespecification S1. Also, the user 3 generates via the user account 3 acircuit design schematic SCH3 based on the specification S1. Moreover,tests are run on the circuit design schematics SCH1 through SCH3 togenerate simulation reports. For example, the design simulation reportgenerator tool 184 (FIG. 3) runs one or more simulations on the circuitdesign schematics SCH1 through SCH3 generated based on the specificationS1. The design simulation report generator tool 184 determines that thecircuit design schematics SCH1 and SCH2 passes the one or moresimulations and the circuit design schematic SCH3 fails the one or moresimulations. This determination is a completion of a frontend process,which occurs at a stage 3 of the design engineering process 930. Themanagement server 152 indicates the rejection of the circuit designschematic SCH3 to the user account 3 that is accessed by the user 3 tocreate the circuit design schematic SCH3.

The simulation reports include whether the circuit design schematicsSCH1 through SCH3 pass or fail the tests. The simulation reports aresent from the design simulation report generator tool 184 of FIG. 3 viathe computer network 110 and the requester account 1 to the requestercomputing device 1. The requester 1 views the simulation reportsdisplayed on the display device of the requester computing device 1 viathe requester account 1 to select the simulation reports for the circuitdesign schematics SCH1 and SCH2.

The selection of the simulation reports for the circuit designschematics SCH1 and SCH2 is sent from the requester computing device 1via the requester account 1 and the computer network 110 to themanagement server 152. The management server 152 indicates the selectionto the user accounts 1 and 2. The user 1 views the selection of thecircuit design schematic SCH1 posted to the user account 1 and generatesa layout design from the circuit design schematic SCH1. Similarly, theuser 1 views the selection of the circuit design schematic SCH2 postedto the user account 2 and generates a layout design from the circuitdesign schematic SCH2. Furthermore, tests are run on the layout designsto generate multiple signoff reports. For example, the design simulationreport generator tool 184 (FIG. 3) runs one or more simulations on thelayout designs generated from the circuit design schematics SCH1 andSCH2. The design simulation report generator tool 184 determines thatboth the layout designs generated for the circuit design schematics SCH1and SCH2 passes the one or more simulations. This determination is acompletion of a frontend process, which occurs at a stage 4 of thedesign engineering process 930. The signoff reports indicate that thelayout designs generated for the circuit design schematics SCH1 and SCH2passes one or more tests.

The signoff reports are sent from the design simulation report generatortool 184 of FIG. 3 via the computer network 110 and the requesteraccount 1 to the requester computing device 1. The requester 1 views thesignoff reports displayed on the display device of the requestercomputing device 1 via the requester account 1. The requester 1 uses therequester computing device 1 to indicate via the requester account 1that prototypes are to be generated based on the signoff reports for thelayout designs generated from the circuit design schematics SCH1 andSCH2.

Upon receiving the indication that the prototypes are to be generatedfrom the requester computing device 1 via the computer network 110, theshuttle manager tool 302 (FIG. 3) of the online design engineeringsystem 102 provides a file including the layout design for the circuitdesign schematic SCH1, a file including the circuit design schematicSCH1, and a file including the specification S1 via the computer network110 and the fabrication entity account 1 to the fabrication computingdevice 1. Moreover, the shuttle manager tool 302 of the online designengineering system 102 provides a file including the layout design forthe circuit design schematic SCH2, a file including the circuit designschematic SCH2, and a file including the specification S1 via thecomputer network 110 and the fabrication entity account 1 to thefabrication computing device 1. At a stage 5 of the design engineeringprocess 930, the fabrication entity 1 fabricates a prototype of theintegrated circuit chip from the layout design generated from thecircuit design schematic SCH1, and sends the prototype via the mailingservice to the design engineering entity. Moreover, at the stage 5 ofthe design engineering process 930, the fabrication entity 1 fabricatesa prototype of the integrated circuit chip from the layout designgenerated from the circuit design schematic SCH2, and sends theprototype via the mailing service to the design engineering entity. Uponreceiving the prototypes for the circuit design schematics SCH1 and SCH2from the fabrication entity 1, the prototype tester and test reportgenerator tool 306 (FIG. 3) is executed by the design engineering entityto test the prototypes to validate or invalidate the prototypes. Thevalidation or invalidation is performed at a stage 6 of the designengineering process 930. Upon determining that the prototype generatedfrom the circuit design schematic SCH1 is valid, at a stage 7 of thedesign engineering process 930, the prototype is sent by the designengineering entity via the mailing service to the fabrication entity 1for fabricating integrated circuit chips based on the prototype. On theother hand, upon determining that the prototype generated from thecircuit design schematic SCH2 is invalid, the prototype is not sent bythe design engineering entity via the mailing service to the fabricationentity 1. The management server 152 indicates the invalidation of theprototype generated from the circuit design schematic SCH2 to the useraccount 2 that is accessed by the user 2 to create the layout designfrom which the prototype is fabricated.

In one embodiment, upon determining that the prototype generated fromthe circuit design schematic SCH2 is invalid, the prototype tester andtest report generator tool 306 indicates the invalidity to the useraccount 2 via the computer network 110. The user 2 changes the layoutdesign generated from the circuit design schematic SCH2 to generate achanged layout design. The changed layout design is tested in the samemanner in which the layout design generated from the circuit designschematic SCH2 is tested. Moreover, after passing the test, themanagement server 152 determines to store the changed layout design inthe design database 160 for access by the user accounts 1 through N. Inan embodiment, the changed layout design is obfuscated, in a mannerdescribed above, before being displayed within the user account 1 andthe user accounts 3 through N based on whether the user 2 has indicatedthe changed layout design to be private or public.

It should be noted, that in an embodiment, at the end of the stage 3 ofthe design engineering process 930, a deposit account assigned to therequester 1 is debited by the credit and debit server system accordingto a predetermined percentage, e.g., 30%, etc., of a total cost, e.g.,100%, etc., of creating designs and fabricating integrated circuit chipsfrom a prototype of one of the designs. The deposit account is debitedfor crediting by the credit and debit server system the predeterminedpercentage to the deposit accounts of the users 1, 2, and 3 thatgenerated the circuit design schematics SCH1 through SCH3. Moreover, atthe end of the stage 6 of the design engineering process 930, a depositaccount of the requester 1 is debited by the credit and debit serversystem according to another predetermined percentage, e.g., 30%, etc.,of the total cost. The deposit account is debited for crediting by thecredit and debit server system the other predetermined percentage todeposit accounts of the user 1 that generated the layout design based onthe circuit design schematic SCH1 for which the prototype is validated.Also, at the end of the stage 7 of the design engineering process 930, adeposit account of the requester 1 is debited by the credit and debitserver system according to yet another predetermined percentage, e.g.,10%, etc., of the total cost. The deposit account is debited forcrediting by the credit and debit server system the yet otherpredetermined percentage to a deposit account of the user 1 thatgenerated the layout design generated from the circuit design schematicSCH1 for which the integrated circuit chips are fabricated at the stage7 of the design engineering process 930.

FIG. 10 is a diagram of an embodiment of a specification 1002 of acomponent of the electrical circuit. Examples of parameters of thespecification 1002 include a minimum value and the maximum value of anoperating voltage provided as an input to the electrical circuit, amaximum value of an input quiescent current, a minimum value of acurrent output from the electrical circuit, and an amount of shortcircuit current output from the electrical circuit.

FIG. 11 is a diagram of an embodiment of a system 1100 to illustratethat the online design engineering system 102 provides access to theusers 1 through N via the user accounts 1 through N for generating adesign and fabrication of an integrated circuit from the design. Arequest for a prototype of an integrated circuit chip is provided by therequester 1 via the requester computing device 1 and the computernetwork 110 to the online design engineering system 102. Upon receivingthe request, the online design engineering system 102 offers variousadvantages, such as, searching of the searchable storage 162 that hasvarious designs; a trial, such as tests, of a design or a prototype ofan integrated circuit chip before mass production of the integratedcircuit chip; generation of a derivative of an integrated circuit chipdesign by coupling one design instead of another design with theintegration circuit design 452; direct designer support provided via theuser accounts 1 through N and the online design engineering system 102by the corresponding users 1 through N to the requester 1 during eachstage of generating a prototype of an integrated circuit chip; and ascalable and focused research and development. A prototype of anintegrated circuit chip is fabricated in a fab, which is controlled bythe one or more fabrication entities, described herein. The onlinedesign engineering system 102 provides a review of the prototype whenthe prototype tester and test report generator tool 306 (FIG. 3)executes a test on the prototype.

FIG. 12 is a diagram of an embodiment of a system 1200 to illustrate aninterplay between the requester 1, sometimes referred to herein as acustomer, and the community to fabricate a prototype of an integratedcircuit chip. Examples of the customer include startup companies,product companies, and a small and midsize business (SMB), etc. Examplesof the community include designers of circuit designs, developers ofintegrated circuit chips, testers of designs, testers of prototypes ofintegrated circuit chips, customers who request designs and/orprototypes of integrated circuit chips, foundry entities, and marketersof designs and/or integrated circuit chips. The customer submits arequest for a prototype of an integrated circuit chip via the onlinedesign engineering system 102 to the community. The community respondsto the request via the online design engineering system 102 with aprototype of an integrated circuit chip for review by the customer.

FIG. 13A is a diagram of an embodiment of a design engineering method1300 that is executed by the online design engineering system 102. Therequester 1, such as an integrated circuit provider or an integratedcircuit developer or an IoT developer or an SoC developer, uses therequester computing device 1 to send a specification, via the requesteraccount 1, for generating a design to the online design engineeringsystem 102. For example, the requester 1 uses the requester computingdevice 1 to access the requester account 1 via the website to post onthe requester account 1 a request for generating an integrated circuitchip design and the specification. The specification includes features,such as the parameters, of a design, costs of generating the integratedcircuit chip design, and a schedule for generating the integratedcircuit chip design.

Upon receiving the request and the specification, the management server152 searches the design database 160 for a design that forms a portion,such as a component design, of the integrated circuit chip design.Moreover, the management server 152 searches a database of a thirdparty, who is not a requester or a user, to determine that the databaseincludes a design that forms another portion, such as a componentdesign, of the integrated circuit chip design. The management server 152determines that an additional portion, such as an additional componentdesign, of the integrated circuit chip design is to be generated. Themanagement server 152 posts the request and the specification to theuser accounts 1 through N in addition to a request for generating theadditional portion of the integrated circuit chip design. The users 1through N use the corresponding computing devices 1 through N to accessthe corresponding, such as respective, user accounts 1 through N. Adesign generated by the user 1 by applying the online design engineeringsystem 102 passes simulation tests described herein as being executedvia the online design engineering system 102 and the design is theadditional portion of the integrated circuit chip design.

The management server 152 determines whether the requester 2 hasprovided, via the requester account 2, parameters of a specificationthat are met by the additional portion. Upon determining so, themanagement server 152 notifies the requester 2 via the computer network110 and the requester account 2 of availability of the additionalportion.

FIG. 13B is a diagram of an embodiment of a continuation of the designengineering method 1300 of FIG. 13A. As shown in FIG. 13B, uponreceiving the request for the integrated circuit chip design from therequester 1 via the requester account 1, the design competitiongenerator tool 310 posts a competition for generating the additionalportion of the integrated circuit chip design. For example, thecompetition is posted by the design competition generator tool 310 on awebpage that is accessed via the website. The webpage is accessed uponaccessing any of the user accounts 1 through N. Along with the postingof the competition, the specification of the integrated circuit chipdesign and the request for the integrated circuit chip design are postedby the design competition generator tool 310 on the webpage. Results ofthe competition and a winner, e.g., the user 1, etc., of the competitionare posted by the design competition generator tool 310 on the webpage.Once the additional portion of the integrated circuit chip design haswon the competition, such as by passing one or more simulation testsdescribed herein, the additional portion or the entire integratedcircuit chip design is stored within the searchable storage 162.Members, such as the users 2 through N, submit bids via correspondinguser accounts 2 through N or the requester 2 submits bids via therequester account 2 for the additional portion or the entire integratedcircuit chip design. The bids are sent to the user account 1 that isaccessed by the user 1 to generate the additional portion. The user 1uses the user computing device 1 to access the user account 1 to acceptone of the bids. An indication of the acceptance of one of the bids issent from the user computing device 1 via the user account 1 and thecomputing device 110 to the one of the user computing devices 2 throughN via the corresponding user accounts 2 through N or the requestercomputing device 2 via the requester account 2. The credit and debitserver system debits an amount of the bid that is accepted from adeposit account of the requester 2 or one of the users 2 through N andcredits the amount to a deposit account of the user 1.

FIG. 13C is a diagram of an embodiment of a continuation of the designengineering method 1300 to illustrate functionality of the online designengineering system 102. The design project searcher tool 330 (FIG. 3)allows the users 1 through N via the corresponding user accounts 1through N to search the project database of the online designengineering system 102 connected to the management server 152 for anyprojects, such as incomplete projects, for generating designs ofintegrated circuits. The projects are posted by the requesters 1 and 2via corresponding requester accounts 1 and 2 to the website. Forexample, a project includes a specification for a design or parametersfor generating the design. The specification is accessed by the designproject searcher tool 300 from a name of an integrated circuit that isprovided by one of the users 1 through N via corresponding user account1 through N to search for a project. For example, the user 1 uses theuser computing device 1 to access the website to further access the useraccount 1. The user 1 enters a name of the integrated circuit within aproject search field displayed on the display device of the usercomputing device 1 by the management server 152, and selects a submitoption, such as a submit button, displayed besides the project searchfield. Upon receiving the name of the integrated circuit, the designproject searcher tool 330 determines whether the received name matches aname, such as a name of the integrated circuit, within a specificationfor a design to be generated. In response to determining that thereceived name matches the name within the specification, the designproject searcher tool 330 accesses the project and sends the projectwith the specification via the computer network 110 to the usercomputing device 1 for access of the specification by the user 1 via theuser account 1. In an embodiment, in addition to a specification for adesign of an integrated circuit, the requester 1 posts using therequester account 1 to the website skills and/or expertise of a designerwho will generate the design.

When the additional portion of the integrated circuit chip design passesone or more simulation tests described herein, such as one beingconducted by the local test bench tool 165, and/or the circuit designverification tool 188, and/or the local layout verification tool 167,and/or the layout design verification tool 190, the management server152 certifies the additional portion and stores the additional portionin the design database 160. Moreover, on the other hand, when theadditional portion of the integrated circuit chip design does not passthe one or more simulation tests described herein, the management server152 provides the additional portion to the user account 1 and indicatesthat the additional portion did not pass the one or more simulationtests.

Moreover, in an embodiment, when the additional portion passes a costthreshold that is set by the requester 1 via the requester account 1 forfabricating an integrated circuit chip having the additional portion,the management server 152 stores the additional portion in the designdatabase 160. For example, the additional portion passes the costthreshold when the management server 152 determines a cost offabricating the integrated chip having the additional portion is lessthan or equal to a pre-determined cost. On the other hand, when theadditional portion fails the cost threshold that is set by the requester1 via the requester account 1, the management server 152 provides theadditional portion to the user account 1 and indicates that theadditional portion did not meet the cost threshold. For example, theadditional portion fails the cost threshold when the management server152 determines a cost of fabricating the integrated chip having theadditional portion is greater than a pre-determined cost.

In this embodiment, each component of the additional portion isassociated with a pre-determined cost, which is stored in the searchablestorage 162. The management server accesses the pre-determined costs andsums the costs of the components of the additional portion to determinea total cost of the additional portion to further determine whether theadditional portion meets the cost threshold. For example, if the sumexceeds the cost threshold, the management server 152 determines thatthe cost threshold is exceeded and is not met. On the other hand, if thesum does not exceed the cost threshold, the management server 152determines that the cost threshold is not exceeded and is met.

FIG. 14A is a diagram illustrating the flow of a design engineeringmethod 1400 that is executed using the online design engineering system102. The customer, such as the requester 1, who wishes to obtain aprototype of an integrated circuit chip sends a request from therequester computing device 1 via the requester account 1 and thecomputer network 110 to the online design engineering system 102 for adesign of the prototype of the integrated circuit chip. For example, thecustomer submits a specification to the management server 152 foruploading and posting to the searchable storage 162. The design searchertool 322 searches within an in product store, such as the designdatabase 160, to determine based on the specification whether a designthat satisfies the parameters of the specification is stored in thedesign database 160. Upon determining that the design satisfies theparameters, the design searcher tool 322 provides an indication via thecomputer network 110 and the requester account 1 to the customer of thedesign. When the indication is sent, the obfuscator tool 182 obfuscatesone or more portions of the design upon determining that the design isdesignated as private by a designer, such as the user 1, of the design.An order for a prototype of the integrated circuit chip based on thedesign is sent from the requester computing device 1 via the requesteraccount 1 to the fabrication entity account 1 for fabrication of theprototype. The fabrication entity 1 operates the fabrication computingdevice 1 to access the fabrication entity account 1 to receive theorder.

On the other hand, upon determining that none of the designs storedwithin the design database 160 match the parameters of thespecification, the design searcher tool 322 sends a request for thedesign and the specification via the fabrication entity account 1 andthe computer network 110 to the fabrication computing device 1controlled by the fabrication entity 1. The fabrication computing device1 is operated by the fabrication entity 1 to search an IP library thatis accessible to the fabrication entity 1 but not to the designengineering entity. Moreover, fabrication computing device 1 is operatedby the fabrication entity 1 to access the design database 160 via thefabrication entity account 1. Upon accessing the design database 160,the fabrication entity 1 operates the fabrication computing device 1 tosearch the design database 160 for the design to determine whether thedesign is stored in the design database 160. Upon determining that thedesign is stored in the IP library or in the design database 160, thefabrication computing device 1 provides an indication to the managementserver 152 via the computer network 110 and the fabrication entityaccount 1 of the design. The management server 152 forwards theindication of the design to the requester 1 via the computer network 110and the requester account 1. Upon receiving the indication, an order fora prototype of the integrated circuit chip based on the design is sentfrom the requester computing device 1 via the requester account 1 to thefabrication entity account 1 for fabrication of the prototype. On theother hand, upon receiving a determination from the fabricationcomputing device 1 via the fabrication entity account 1 and the computernetwork 110 that the design of the integrated circuit chip is not storedin the IP library and in the design database 160, the project postertool 330 of the online design engineering system 102 posts a project forgenerating the design of the integrated circuit chip.

In one embodiment, upon determining that none of the designs storedwithin the design database 160 match the parameters of thespecification, the management server 152 sends a request via the useraccounts 1 through N of the community to the user computing devices 1through N for determining whether any of the users 1 through N haveknowledge of the design based on the specification. The users 1 throughN operate the corresponding user computing devices 1 through N torespond to the request regarding the knowledge of the design viacorresponding user accounts 1 through N and the computer network 110 tothe management server 152. The management server 152 sends the responseof the users 1 through N via the computer network 110 and the requesteraccount 1 to the requester computing device 1.

Moreover, upon receiving a determination from the fabrication computingdevice 1 via the fabrication entity account 1 and the computing network110 that the design is not feasible, such as more work on the design isto be done, or the design exceeds the cost threshold, or that the designfails one of more simulation tests, or a combination thereof, theproject poster tool 330 (FIG. 3) of the online design engineering system102 posts a project to make the design feasible. The project is postedon the website and is accessed by the users 1 through N via the usercomputing devices 1 through N and the user accounts 1 through N and thecomputer network 110.

In one embodiment, the customer, who wishes to learn more about theintegrated circuit chip, posts a problem or a question regarding adesign of an integrated circuit chip or a question regarding a designerof the integrated circuit chip to the online design engineering system102 so that one or more of the users 1 through N via corresponding oneor more of the user accounts 1 through N provide a solution to theproblem or an answer to the questions. For example, the requester 1 usesthe requester computing device 1 to post via the computer network 110and the requester account 1 the problem on the website. The users 1through N use the user computing devices 1 through N to access theproblem via the user accounts 1 through N and the computer network 110.The users 1 through N use the user computing devices 1 through N toprovide feedback or a comment to the problem to the requester computingdevice 1 via the user accounts 1 through N and the computer network 110.An example of the question regarding the designer is one inquiring abouta skill set of the designer for generating a design of an integratedcircuit chip.

In an embodiment, the management server 152 searches one or more of thevarious databases described herein, such as the design database 160, thespecification database 104, the comment database 204, to provide aresponse to the problem or the question. The management server 152 sendsthe response to the requester computing device 1 via the computernetwork 110 and the requester account 1.

FIG. 14B is a diagram of an embodiment of a flow of a design engineeringprocess 1410 to illustrate an interaction of the user 1 with a display1420, such as an image or a user interface, on a display device of theuser computing device 1. The display 1420 is generated on the usercomputing device 1 that is operated by the user 1 and shows details thatare accessed via the user account 1. For example, the details includes aname of the user 1; a title within an organization in which the user 1is an employee, or an owner, or a contractor; skills and competencies ofthe user 1 for generating a design or for using a set of design tools;and types of components for which the user 1 has expertise in designing.Moreover, in this example, the user account 1 includes projects that arecompleted by the user 1 or are accepted by the user 1 via the useraccount 1, additional information about the user 1, tutorials that theuser 1 has posted to the user account 1 and/or reviewed via the useraccount 1.

The user 1 registers with the online design engineering system 102 bybeing assigned login information, e.g., user identification, userpassword, etc., by the authenticator tool 332 of the online designengineering system 102. The login information that is assigned to theuser account 1 is unique to the user account 1 in that the logininformation cannot be used to access another one of the user accounts 2through N or the requester accounts 1 and 2 or the fabrication entityaccounts 1 and 2. The user 1 logs into the user account 1 to look forprojects. For example, the user 1 uses the computing device 1 to loginto the user account 1 and provides an indication along with projectsearching criteria, such as a name of an integrated circuit, to theproject searcher tool 330 of the online design engineering system 102via the computer network 110. The project searching criteria is for aproject for generating a circuit design. Examples of the name of anintegrated circuit include an adder, a half adder, a flip flop, adecoder, and an encoder. Upon receiving the indication, the projectsearcher tool 330 searches the project database for one or moreprojects, such as an incomplete project, that match the projectsearching criteria. The project searcher tool 330 sends the project,such as a specification having a name that matches the name receivedwithin the project searching criteria, via the computer network 110 andthe user account 1 to the user computing device 1.

The user 1 logs into the user account 1 by using the user computingdevice 1 and answers a question that is posted on the website by therequester 1 via the requester computing device 1 and the requesteraccount 1. Within the user account 1, results of a simulation test, suchas test conducted on a design that is created by the user 1, are postedby the management server 152.

Moreover, the user 1 logs into the user account 1 by operating the usercomputing device 1 and creates a design by using the design tools 158,described herein, tests the design, and stores the design within thedesign database 160. The design is certified by the automaticcertification server 112 after passing one or more simulation tests.

The online design engineering system 102 stores information within animplementation database of the online design engineering system 102. Theimplementation database is stored within the searchable storage 162stores the information regarding successful implementations of one ormore integrated circuit chip designs and a first successfulimplementation of an integrated circuit chip design. For example, themanagement server 152 determines a number of integrated circuit chipsthat implement a design that is generated via the online designengineering system 102 and stores the number within the implementationdatabase. The number of the integrated circuit chips is a number ofimplementations of the design. As another example, the management server152 determines a date on which a design is implemented within anintegrated circuit chip for a first time and identifies a user accountof a user that created the design and stores the date and the useraccount identifier, such as a number or a series of alphanumericcharacters, within the implementation database.

FIG. 15 is a diagram to illustrate creation of a design, such as adesign of a digital circuit and a design of an analog circuit. Registertransfer level (RTL), which is a language stored in the circuit designtool database 206, is an example of the circuit design tool 162 that isaccessed by the one or more users 1 through N via the corresponding,such as respective, one or more user accounts 1 through N, the computernetwork 110, and the corresponding one or more user computing devices 1through N to model a circuit in terms of flow of data between registersand logical operations performed on the data. For example, the RTLlanguage is used to generate a circuit design based on a specification.An RTL description is usually converted into a gate level description ofthe circuit design by a logic synthesis tool, which is an example of thecircuit design tool 162 stored in the circuit design tool database 206.For example, the user 1 uses the user computing device 1 to access theuser account 1 via the computer network 110 and indicate to themanagement server 152 that the logic synthesis tool is to be executed.Upon receiving the indication, the management server 152 executes thelogic synthesis tool to generate the gate level description. The gatelevel description is accessed by the user 1 via the user account 1 byusing the user computing device 1. In addition to the gate leveldescription, the layout design tool 166 is accessed by the usercomputing device 1 via the user account 1 to generate a layout design ofa subchip, such as a component, of an integrated circuit chip.

Similarly, in an analog circuit design, a system model is generatedusing the design tools 158. From the system model, a schematic of acircuit design of an analog circuit is generated by using the circuitdesign tool 164. From the top-level schematic, a top-level layout designof the analog circuit is generated by using the layout design tool 166.

FIG. 16 is a diagram of an embodiment of a design engineering method1600. In the design engineering method 1600, the requester 1 operatesthe requester computing device 1 to provide a data sheet 1602 havingmultiple parameters of a specification via the requester account 1 andthe computer network 110 to the management server 152. Moreover, once acircuit design is generated by the user 1 via the user account 1 basedon the data sheet 1602, the user 1 uses the user computing device 1 toaccess the local test bench tool 165 from the automatic certificationserver 112. In one embodiment, the local test bench tool 165 is storedin a memory device of the user computer device 1 but is not downloadedfrom the automatic certification server 112 via the computer network110. Moreover, the user 1 uses the user computing device 1 to indicatevia the user account 1 to the design engineering entity to test thecircuit design. Upon receiving the indication, the automaticcertification server 112 executes the circuit design verification tool188 to test the circuit design. Upon determining that the circuit designpasses the test, the automatic certification server 112 issues acertificate indicating the same and sends the certificate via thecomputer network 110 to the user account 1 for access by the user 1 viathe user computing device 1. Moreover, the certificate indicating thatthe circuit design passed the test is stored within the searchablestorage 162 and is associated, such as linked or mapped, with the useraccount 1 in the searchable storage 162. The association of thecertificate indicating that the circuit design passed the test and theuser account 1 is performed by the management server 152. When therequester 1 operates the requester computing device 1 to access thecircuit design, the management server 152 accesses the certificateindicating that the circuit design passed the test and sends thecertificate via the computer network 110 to the requester computingdevice 1 for display of the certificate via the requester account 1. Thetest conducted by the design engineering entity provides an independentverification of the circuit design. The dual verification of the circuitdesign by the user 1 and the design engineering entity increasescoverage and confidence in the circuit design.

Similarly, once a layout design is generated from the circuit design bythe user 1 via the user account 1, the user 1 uses the user computingdevice 1 to access the local layout verification tool 167 from theautomatic certification server 112. In one embodiment, the local layoutverification tool 167 is stored in a memory device of the user computerdevice 1 but is not downloaded from the automatic certification server112 via the computer network 110. Moreover, the user 1 uses the usercomputing device 1 to indicate via the user account 1 to the designengineering entity to test the layout design. Upon receiving theindication, the automatic certification server 112 executes the layoutdesign verification tool 190 to test the layout design. Upon determiningthat the layout design passes the test, the automatic certificationserver 112 issues a certificate indicating the same and sends thecertificate via the computer network 110 to the user account 1 foraccess by the user 1 via the user computing device 1. Moreover, thecertificate indicating that the layout design passed the test is storedwithin the searchable storage 162 and is associated, such as linked ormapped, with the user account 1 in the searchable storage 162. Theassociation of the certificate indicating that the layout design passedthe test and the user account 1 is performed by the management server152. When the requester 1 operates the requester computing device 1 toaccess the layout design, the management server 152 accesses thecertificate indicating that the layout design passed the test and sendsthe certificate via the computer network 110 to the requester computingdevice 1 for display of the certificate via the requester account 1. Thetest conducted by the design engineering entity provides an independentverification of the layout design. The dual verification of the layoutdesign by the user 1 and the design engineering entity increasescoverage and confidence in the layout design.

Furthermore, once a prototype of an integrated circuit is generated fromthe layout design and sent by the fabrication entity 1 to the user 1 viathe mailing service, the user 1 uses the user computing device 1 toaccess a local test silicon tool 1604 from the automatic certificationserver 112. The automatic certification server 152 does not allow adownload of the local test silicon tool 1604 via the computer network110 to the computing device 1 operated by the user 1. As such, the localtest silicon tool 1604 is executed on the cloud computing node. In oneembodiment, the local test silicon tool 1604 is stored in a memorydevice of the user computer device 1 but is not downloaded from theautomatic certification server 112 via the computer network 110.

Moreover, the user 1 uses the user computing device 1 to indicate viathe user account 1 to the design engineering entity to test theprototype, which is sent from the user to the design engineering entityvia the mailing service or is sent from the fabrication entity 1 to thedesign engineering entity via the mailing service. Upon receiving theindication, the automatic certification server 112 executes theprototype tester and test report generator 306 to test the prototype.Upon determining that the prototype passes the test, the automaticcertification server 112 issues a certificate indicating the same andsends the certificate via the computer network 110 to the user account 1for access by the user 1 via the user computing device 1. Moreover, thecertificate indicating that the prototype passed the test is storedwithin the searchable storage 162 and is associated, such as linked ormapped, with the user account 1 in the searchable storage 162. Theassociation of the certificate indicating that the prototype passed thetest and the user account 1 is performed by the management server 152.When the requester 1 operates the requester computing device 1 to accessthe circuit design or the layout design, the management server 152accesses the certificate indicating that the prototype passed the testand sends the certificate via the computer network 110 to the requestercomputing device 1 for display of the certificate via the requesteraccount 1. The test conducted by the design engineering entity providesan independent validation of the prototype. The dual validation by theuser 1 and the design engineering entity increases coverage andconfidence in the prototype.

The use counter tool 312 (FIG. 3) of the design engineering entity 102counts a number of implementations of a design within one or moreintegrated circuits. Moreover, the design rating generator tool 192(FIG. 3) generates ratings of the design. For example, a first designfor which the use counter tool 312 determines to have a greater numberof uses, such as a number of times for which the design is implementedin one or more integrated circuits, compared to a second design, thefirst design is assigned a higher rating than the second design. Itshould be noted that with an increase in a number of times of use of thedesign in an integrated circuit, e.g., a graphics processor, a gamingprocessor, a display processor, an operating system processor, etc.,confidence in the design by the community increases.

FIG. 17 is a diagram used to illustrate a relationship betweenspecification parameters coverage by a design and confidence of thecommunity, requesters and fabrication entities in the design. As thedesign progresses through stages, e.g., circuit design test, layoutdesign test, prototype test, integrated circuit use, etc., coverage ofspecification parameters of the data sheet 1602 increases. Moreover, asa number of uses of the design increases, confidence of the communityand requesters and fabrication entities for the design increases andratings of the design increase. It should be noted that a number of usesof the design increases by implementing the design in integratedcircuits having different applications and/or by implementing the designfor a large number of times in integrated circuits having the sameapplication. Examples of the different applications include a mobileapplication, a computer application, a sensor application, and an IoTapplication.

FIGS. 18A-1, 18A-2, 18A-3, 18A-4, and 18A-5 are diagrams of anembodiment of a design engineering method 1800 to illustrate a creationof the data sheet 1602. In an operation 1 of the design engineeringmethod 1800, the requester 1 uses the requester computing device 1 toaccess the requester account 1 to submit a request for a design of anintegrated circuit. For example, the requester 1 selects an option, suchas a graphical display button, displayed within the requester account 1to submit the request for the design of the integrated circuit via therequester account 1 and the computer network 110 to the data sheetbuilder tool 318 (FIG. 3). In one embodiment, a fabrication entity usesthe fabrication computing device 1 to access the fabrication entityaccount 1 to submit a request for the design of the integrated circuit.The request is submitted via the computer network 110 to the managementserver 152.

In an operation 2 of the design engineering method 1800, upon receivingthe request for the integrated circuit, the data sheet builder tool 318accesses the data sheet 1602 from the template database and providesaccess to the data sheet 1602 to the requester computing device 1 viathe requester account 1 and the computer network 110. The requester 1accesses the data sheet 1602 upon accessing the website and logging intothe requester account 1. The data sheet 1602 includes multiple fieldsfor entry, such as a name of a design of the integrated circuit, globalconditions for the design, and the parameters of the design.

In an operation 3 of the design engineering method 1800, the requester 1fills in parameters of the specification into the data sheet 1602 andselects a submit option, such as a submit button displayed on thedisplay device of the requester computing device 1. The selection of thesubmit option is received by the data sheet builder tool 318 via therequester account 1 and the computer network 110. For example, therequester 1 uses the input device of the requester computing device 1 toprovide the parameters within the fields. As an illustration, therequester 1 provides a single design method for testing the design. Asanother illustration, the requester 1 provides various design methodsfor testing the design. One of the design methods includes a first setof values of the parameters, such maximum and minimum input voltages atan input pin of the design, maximum and minimum output voltages at anoutput pin of the design, maximum and minimum input currents at an inputpin of the design, maximum and minimum output currents at an output pinof the design, and minimum and maximum temperatures of operation of aprototype of the design. Another one of the design methods includes asecond set of values of the parameters. At least one of the values ofthe second set is different one or more corresponding values of thefirst set. For example, the first set has a minimum value of 0 volts atan input pin and a maximum value of 10 volts at the input pin. Thesecond set has a minimum value of 2 volts at the input pin and a maximumvalue of 10 volts at the input pin. As another example, the first sethas a minimum value of 0 volts at the input pin and a maximum value of10 volts at the input pin. The second set has a minimum value of 2 voltsat the input pin and a maximum value of 12 volts at the input pin.

In one embodiment, once the first set of parameters are filled in by therequester 1 into the data sheet 1602 and are received from the requester1 via the requester account 1 and the computer network 110, the datasheet builder tool 318 generates the second set of parameters togenerate another different design method for testing the design. Thedata sheet builder tool 318 populates the data sheet 1602 with thesecond set and sends the data sheet 1602 via the computer network 110and the requester account 1 to the requester computing device 1.

Upon receiving the parameters for the design, in an operation 4 of thedesign engineering method 1800, the data sheet builder tool 318generates a testbench schematic drawing 1806 to execute each test methodfor testing the design of the integrated circuit. For example, the datasheet builder tool 318 generates a first testbench schematic drawing toexecute a first test method for testing the design of the integratedcircuit. As another example, the data sheet builder tool 318 generates asecond testbench schematic drawing to execute a second test method fortesting the design of the integrated circuit. In the second test method,one or more values, such as minimum and maximum values, of a parameterare different than one or more values, such as minimum and maximumvalues, of the parameter in the first test method for testing thedesign. To illustrate, the data sheet builder tool 318 generates a blockhaving pin inputs and pin outputs of the design. To further illustrate,a pin input of the block receives data and a pin out of the blockprovides data as an output result based on the data received at the pininput. Moreover, the data sheet builder tool 318 couples a power supply,such as a voltage power source or a current power source or a signaldriver, to a pin input of the block for receiving power and couples aload, such as resistors and capacitors, to a pin output of the block.Moreover, the testbench schematic drawing 1806 has a reference to aninstantiation value, such as a voltage or a current value, for providingto the pin input of the block. For example, when the testbench schematicdrawing 1806 is accessed via an account, such as a user account or arequester account, for execution of a simulation, the management server152 reads the instantiation value from a memory location in thesearchable storage 162 and applies the instantiation value to a pininput of the testbench schematic drawing 1806 to execute the simulation.To illustrate, there is a pointer from a memory location of thesearchable storage 162 in which the testbench schematic drawing 1806 isstored to a memory location of the searchable storage 162 at which theinstantiation value is stored. When the memory location of thesearchable storage 162 in which the testbench schematic drawing 1806 isaccessed by the management server 152, the pointer points the managementserver 152 to the memory location of the searchable storage 162 at whichthe instantiation value is stored.

The testbench schematic drawing 1806 includes the block, the pin inputs,the pin outputs, the power supply, and the load. Moreover, the testbenchschematic drawing 1806 includes a resistor having a resistance R and acapacitor having a capacitance C. The testbench schematic drawing 1806further includes an analysis to be performed to execute the test methodto generate measurements of electrical parameters at one or more pinoutputs of the block. For example, the test schematic drawing 1806 hasvalues of the power supply to be provided to the pin input, and valuesof the resistor and the capacitor. In addition, the testbench schematicdrawing 1806 has an order of execution of provision of the value of thepower supply and the values of the resistor and the capacitor. Forexample, first the resistor is instantiated to the resistance R and thecapacitor is instantiated to the capacitance C. Then, the power supplyis instantiated to supply a voltage value V1 or a current value I1 or tosupply an amount of power V1*I1. The power supply is to thereaftersupply a voltage value V2 or a current value I2 or to supply an amountof power V2*I2 or to supply an amount of power V1*I2 or to supply anamount of power V2*I1. The value V1 is different from the value V2 andthe value I1 is different from the value I2.

The requester 1 uses the requester computing device 1 to access via therequester account 1 the workspace application 180. The workspaceapplication 180 further provides the requester account 1 access to thetestbench schematic drawing 1806 from the searchable storage 162. Thetestbench schematic drawing 1806 is displayed within a customerworkspace, which is a user interface that is generated on the displaydevice of the requester computing device 1 by execution of the workspaceapplication 180.

In an operation 5 of the design engineering method 1800, the data sheet1602 including the parameters of the specification are stored by themanagement server 152 into the searchable storage 162. For example, thedata sheet 1602 is stored within the specification database 104. Toillustrate, the data sheet 1602 is stored as a specification file, suchas a JavaScript Object Notation (JSON) file, within the specificationdatabase 104. The parameters filled into the data sheet 1602 are anexample of the specification S1.

Moreover, in an operation 6 of the design engineering method 1800, thetestbench schematic drawing 1806 is stored in the specification database104 as a schematic drawing file, and the schematic drawing file isreferred to in the specification file in which the data sheet 1602 isstored. For example, the specification file in which the data sheet 1602is stored includes an identifier, such as a pointer, to a memoryaddress, within the searchable storage 162, at which the schematicdrawing file including the testbench schematic drawing 1806 is stored.As another example, the data sheet builder tool 318 stores the testbenchschematic drawing 1806 within the schematic drawing file and stores theschematic drawing file in the searchable storage 162. In addition, thedata sheet builder tool 318 generates a reference, such as a link, amapping, or an one-to-one association, between the specification file inwhich the data sheet 1602 is stored and the schematic drawing file inwhich the testbench schematic drawing 1806 is stored. To illustrate, thespecification file in which the data sheet 1602 is stored includes apointer to a memory address, of the searchable storage 162, at which theschematic drawing file is stored. As another illustration, the schematicdrawing file in which the testbench schematic drawing 1806 is storedincludes a pointer to a memory address, of the searchable storage 162,at which the specification file is stored.

In an operation 7 of the design engineering method 1800, the user 1 usesthe user computing device 1 to access the data sheet 1602 via thewebsite controlled by the design engineering entity and the useraccount 1. For example, the user 1 accesses the website to access theuser account 1 on which the data sheet 1602 is posted as a designchallenge for the user 1. As another example, the user 1 uses the usercomputing device 1 to access the user account 1 and searches for a nameof a design. Upon receiving the name of the design via the computernetwork 110, the management server 152 provides access to thespecification file by providing data for display of the data sheet 1602having the specification via the computer network 110 to the usercomputing device 1. The specification file includes a reference to theschematic drawing file. As such, in addition to access to the data forthe display of the data sheet 1602 having the specification, themanagement server 152 provides access to the schematic drawing file byproviding data for display of the testbench schematic drawing 1806 viathe computer network 110 to the user computing device 1. Moreover, uponproviding access to the data sheet 1602, the management server 152generates an accept option, such as an accept button, and sends theaccept option via the computer network 110 and the user account 1 todisplay with the data sheet 1602 that is accessed by the user account 1.

In an operation 8 of the design engineering method 1800, the user 1 usesthe input device of the user computing device 1 to select the acceptoption to indicate an acceptance of the design challenge. The selectionof the accept option is received by the data sheet builder tool 318 viathe user account 1 and the computer network 110 from the user computingdevice 1. For example, the data sheet builder tool 318 applies thecommunication protocol to depacketize packets having the selection ofthe accept option and having an identification, such as alphanumericcharacters, of the user account 1 to determine that the user account 1has selected the accept option. Upon receiving the selection of theaccept option via the user account 1 and the computer network 110, thedata sheet builder tool 318, in an operation 9 of the design engineeringmethod 1800, copies to the user account 1 the schematic drawing file inwhich the testbench schematic drawing 1806 is stored and copies to theuser account 1 the specification file in which the data sheet 1602 isstored. To illustrate, when the schematic drawing file and thespecification file are copied to the user account 1, the schematicdrawing file and the specification file are copied to memory addresses,within the searchable storage 162, that are designated by the managementserver 152 to have information associated with, such as related to oraccessible via, the user account 1. At a time the user account 1 isaccessed, the schematic drawing file and the specification file areavailable for access by the user computing device 1 via the computernetwork 110 from the searchable storage 162. The user 1 uses the usercomputing device 1 to log into the user account 1 via the website. Uponaccessing the user account 1, the user 1 has access to the data sheet1602 via the specification file stored within the user account 1 and tothe schematic drawing 1806 via the schematic drawing file stored withinthe user account 1. The testbench schematic drawing 1806 and the datasheet 1602 are displayed within a designer workspace, which is a userinterface that is generated on the display device of the user computingdevice 1 by execution of the workspace application 180.

In one embodiment, instead of or in addition to the resistor and thecapacitor, one or more inductors are used to form the load. For example,the inductor is coupled in series to the resistor or the capacitor or inparallel to the capacitor or the resistor to form the load. In anembodiment, instead of one resistor having the resistance R, thetestbench schematic drawing 1806 has multiple resistors that are coupledto each other in series or in parallel to form the load. Moreover,instead of one capacitor having the capacitance C, the testbenchschematic drawing 1806 has multiple capacitors that are coupled to eachother in series or in parallel to form the load. In one embodiment, thetestbench schematic drawing 1806 is generated upon execution of thelocal test bench tool 165, described above.

In an embodiment, instead of the testbench schematic drawing 1806, anetlist is generated and stored in a netlist file. The netlist is a listof components and a description of connectivity of the components togenerate the testbench schematic drawing 1806. The netlist is stored inthe specification database 104 as a netlist file, and the netlist fileis referred to in the specification file in which the data sheet 1602 isstored. For example, the specification file in which the data sheet 1602is stored includes an identifier, such as a pointer, to a memoryaddress, within the searchable storage 162, at which the netlist fileincluding the netlist is stored. As another example, the data sheetbuilder tool 318 stores the netlist within the netlist file and storesthe netlist file in the searchable storage 162.

FIG. 18B-1 is a diagram to illustrate an embodiment of a continuation ofthe design engineering method 1800 of FIG. 18A-5. Moreover, FIG. 18B-2is a diagram to illustrate an embodiment of a portion of the designengineering method 1800 of FIG. 18B-1. FIG. 18B-3 is a diagram toillustrate an embodiment of another portion of the design engineeringmethod 1800 of FIG. 18B-1. Moreover, FIG. 18B-4 is a diagram toillustrate an embodiment of yet another portion of the designengineering method 1800 of FIG. 18B-1.

In an operation 10 of the design engineering method 1800, the user 1uses the user computing device 1 to log into the user account 1 toaccess the circuit design tool 164 (FIG. 1F) from the circuit designtool database 206 of FIG. 2 to further generate a schematic 1830 of thedesign based on the data sheet 1602. For example, the user 1 uses theinput device of the user computing device 1 to create the schematic 1830by accessing the circuit design tool 164, such as gate designs, orresistor designs, or transistor designs, or inductor designs, orcapacitor designs. The schematic 1830 is displayed within the designerworkspace. In addition, the testbench schematic drawing 1806 and thedata sheet 1602 are displayed within the designer workspace by theworkspace application 180.

In an operation 11 of the design engineering method 1800, the user 1operates the user computing device 1 to access the local test bench tool165 of FIG. 1F from the automatic certification server 112 to test, suchas simulate and characterize, the schematic 1830. For example, the user1 selects a test schematic button on the display device of the usercomputing device 1. Upon receiving the selection of the test schematicbutton via the user account 1 and the computer network 110, theautomatic certification server 112 executes the local test bench tool165 to test the schematic 1830 to generate results of the test. Theresults of the test are not stored by the automatic certification server112 into the searchable storage 162.

In an operation 12 of the design engineering method 1800, the user 1uses the user computing device 1 to upload the schematic 1830 via theuser account 1 and the computer network 110 to the searchable storage162. For example, the user 1 uses the user computing device 1 to selectan upload button displayed on the display device of the user computingdevice 1 to save the schematic 1830 via the user account 1 to thesearchable storage 162. The results of the test that is executed usingthe local test bench tool 165 are not sent from the user computingdevice 1 via the computer network 110 to the searchable storage 162.Moreover, the management server 152, such as the circuit design tool164, upon receiving the selection of the upload button, creates a designfile, such as a JSON file, within the searchable storage 162, stores theschematic 1830 within the design file, and stores the design file withinthe design database 160 of the searchable storage 162. As an example,the design file includes the user login information of the user account1 accessed to create the schematic 1830. In one embodiment, themanagement server 152 generates a reference from the user logininformation of the user account 1 accessed to create the schematic 1830to the design file that includes the schematic 1830. For example, apointer from a memory address of the searchable storage 162 thatincludes the user login information of the user account 1 to a memoryaddress at which the design file including the schematic 1830 is storedin the searchable storage 162 is generated by the management server 152.

The public-private indicator tool 329 generates a public option and aprivate option, both of which are displayed within the designerworkspace along with the schematic 1830. When the user 1 uses the inputdevice of the user computing device 1 to select the public option andsubmits the schematic 1830 via the user account 1 and the computernetwork 110 to the management server 152, the public-private indicatortool 329 receives the selection of the public option via the computernetwork 110. The public-private indicator tool 329 provides theselection of the public option to the obfuscator tool 182. Uponreceiving the selection of the public option from the public-privateindicator tool 329, the schematic 1830 is not obfuscated by theobfuscator tool 182 before being displayed via the user accounts 2through N and the computer network 110 on the display devices of theuser computer devices 2 through N. On the other hand, when the user 1uses the input device of the user computing device 1 to select theprivate option and submits the schematic 1830 via the user account 1 andthe computer network 110 to the management server 152, thepublic-private indicator tool 329 receives the selection of the privateoption via the computer network 110. The public-private indicator tool329 provides the selection of the private option to the obfuscator tool182. Upon receiving the selection of the private option from thepublic-private indicator tool 329, the schematic 1830 is obfuscated bythe obfuscator tool 182 before being displayed via the user accounts 2through N and the computer network 110 on the display devices of theuser computer devices 2 through N.

In one embodiment, the public-private indicator tool 329 provides anaccount identifier option to the user computing device 1 via thecomputer network 110 and the user account 1. The account identifieroption enables the user 1 to select, via the user computing device 1 andthe user account 1, an account, such as a requester account or afabrication entity account or another user account, for which the publicoption or the private option is applied. Upon receiving a selection ofthe account identifier option identifying the account and the selectionof the private option or the public option from the user computingdevice 1 via the user account 1 and the computer network 110, thepublic-private indicator tool 329 stores within the public-privateindicator database 220, a mapping between the account and the selectionof the public option or the private option.

In an operation 13 of the design engineering method 1800, when the user2 or the requester 2 or the fabrication entity 1 requests access to theschematic 1830, the obfuscator tool 182 accesses the public-privateindicator database 220 to determine whether the user account 2 assignedto the user 2 or the requester account 2 assigned to the requester 2 orthe fabrication entity account 1 assigned to the fabrication entity 1 ismapped to the selection of the public option or the private option. Uponidentifying that the user account 2 assigned to the user 2 or therequester account 2 assigned to the requester 2 or the fabricationentity account 1 assigned to the fabrication entity 1 is mapped to theselection of the public option, the obfuscator tool 182 does notobfuscate one or more portions of the schematic 1830 before providingaccess to the schematic 1830 via the user account 2 and the computernetwork 110 to the user computing device 2 or via the requester account2 and the computer network 110 to the requester computing device 2 orvia the fabrication entity account 1 and the computer network 110 to thefabrication computing device 1. On the other hand, upon identifying thatthe user account 2 or the requester account 2 or the fabrication entityaccount 1 is mapped to the selection of the private option, theobfuscator tool 182 obfuscates one or more portions of the schematic1830 to generate an obfuscated schematic design and provides access tothe obfuscated schematic design via the user account 2 and the computernetwork 110 to the user computing device 2 or via the requester account2 and the computer network 110 to the requester computing device 2 orvia the fabrication entity account 1 and the computer network 110 to thefabrication computing device 1.

FIG. 18C-1 is a diagram to illustrate an embodiment of a continuation ofthe design engineering method 1800 of FIG. 18B-4. Moreover, FIG. 18C-2is a diagram to illustrate an embodiment of a portion of the designengineering method 1800 of FIG. 18C-1. FIG. 18C-3 is a diagram toillustrate an embodiment of another portion of the design engineeringmethod 1800 of FIG. 18C-1. Moreover, FIG. 18C-4 is a diagram toillustrate an embodiment of yet another portion of the designengineering method 1800 of FIG. 18C-1. FIG. 18C-5 is a diagram toillustrate an embodiment of another portion of the design engineeringmethod 1800 of FIG. 18C-1. Moreover, FIG. 18C-6 is a diagram toillustrate an embodiment of yet another portion of the designengineering method 1800 of FIG. 18C-1.

In an operation 14 of the design engineering method 1800, the user 1operates the user computing device 1 to access, via the website and theuser account 1, the data sheet 1602 and the block of the testbenchschematic drawing 1806. In one embodiment, in addition to the data sheet1602 and the block, the schematic 1830 is also displayed on the website.When the block and the data sheet 1602 are accessed, the managementserver 152 sends via the computer network 110 a characterize option suchas a characterize button, for display on the display device of the usercomputing device 1.

The user 1 operates the input device of the user computing device 1 toselect the characterize option. Upon receiving the selection of thecharacterize option via the computer network 110 and the user account 1,in an operation 15 of the design engineering method 1800, the automaticcertification server 112 accesses the design file in which the schematic1830 is stored and the specification file in which the data sheet 1602is stored from the searchable storage. The automatic certificationserver 112 parses the design file to access the schematic 1830 andperforms an official characterization, which is a characterization bythe design engineering entity, of the schematic 1830. For example, theautomatic certification server 112 executes the circuit designverification tool 188 of FIG. 1F on the schematic 1830 to determinewhether the schematic 1830 passes or fails a simulation test. Toillustrate, the automatic certification server 112 provides an input,such as an instantiation value, to the schematic 1830 to generate anexpected output and compares the expected output with a desired output,which is pre-stored in the searchable storage 162. Upon determining thatthe expected output matches the desired output, the automaticcertification server 112 determines that the schematic 1830 passes thesimulation test. On the other hand upon determining that the expectedoutput does not match the desired output, the automatic certificationserver 112 determines that the schematic 1830 fails the simulation test.As another illustration, the automatic certification server 112 couplesan input pin, designated an “In” of the schematic 1830 with the powersupply of the testbench schematic drawing 1806 and couples the load toan output pin, labeled as “Out” of the schematic 1830. The automaticcertification server 112 provides the instantiation value at the inputpin to generate the expected output and compares the expected outputwith the desired output to determine whether the testbench schematicdrawing 1806 passes the simulation test.

Upon execution of the simulation test, in an operation 16 of the designengineering method 1800, the data sheet 1602 is accessed from thesearchable storage 162 and is updated by the management server 152 withresults, such as pass or fail, of the simulation test. Other examples ofthe results of the simulation test include a value of the expectedoutput, a value of the input, and a value of the desired output.Moreover, the data sheet 1602, after being updated with the results ofthe simulation test, is stored by the management server as a file, suchas a JSON file, in the searchable storage 162.

In an operation 17 of the design engineering method 1800, based on theresults of the simulation test, the management server 152 determinesthat the schematic 1830 wins the design challenge that is proposed inthe operation 7 of the design engineering method 1800. For example, upondetermining that the schematic 1830 passes the simulation test, themanagement server 152 further determines that the schematic 1830 winsthe design challenge and further allows bidding to occur on theschematic 1830.

In an operation 18 of the design engineering method 1800, other users 2through N, the requester 1, the requester 2, the fabrication entity 1,and/or a fabrication entity 2 access the block representing theschematic 1830 in an obfuscated manner via their respective accounts,such as the user accounts 2 through N, the requester account 1, therequester account 2, the fabrication entity account 1, and thefabrication entity account 2. For example, the user 2 uses the usercomputing device 2 to access the website and the user account 2 tofurther search for a design of an integrated circuit. To illustrate, theuser 2 provides a name of an integrated circuit, such as ananalog-to-digital converter or an oscillator or a phase-locked loop, tosearch for a design of the integrated circuit. The name is sent from theuser computing device 2 via the computer network 110 to the managementserver 152. The design searcher tool 322 determines that the design namewithin the data sheet 1602 matches the name received from the usercomputing device 2.

Upon determining that the design name within the data sheet 1602 matchesthe name received from the user computing device 2, the design searchertool 322 sends a request to the obfuscator tool 182 to access theschematic 1830. The obfuscator tool 182 determines whether the schematic1830 is indicated as private or public in the public-private indicatordatabase 220. Upon determining that the schematic is indicated aspublic, the obfuscator tool 182 does not obfuscate one or more portionsof the schematic 1830 and sends the schematic 1830 via the computernetwork 110 to the user computing device 2 for display within the useraccount 2. On the other hand, upon determining that the schematic isindicated as private, the obfuscator tool 182 obfuscates one or moreportions of the schematic 1830 to generate the block, such as a block1832, and sends the block via the computer network 110 to the usercomputing device 2 for display within the user account 2. In addition tosending the block or the schematic 1830, the management server 152 sendsthe data sheet 1602 via the computer network 110 to the user computingdevice 2 for display within the user account 2. Furthermore, in additionto sending the block or the schematic 1830 and the data sheet 1602, themanagement server 152 sends a bid option, such as a bid button, via thecomputer network 110 to the user computing device 2 for display withinthe user account 2. The user 2 reviews the block or the schematic 1830and the data sheet 1602 on the display device of the user computingdevice 2, and decides whether to bid on a design represented by theblock or the schematic 1830 and the specification within the data sheet1602. Upon determining to bid on the design, the user 2 uses the inputdevice of the user computing device 2 to select the bid option. Uponreceiving the selection of the bid option via the computer network 110and the user account 2, the royalty generator tool 304 of FIG. 3 sendsvia the computer network 110 to the user computing device 2 fields forentry of a dollar amount for the bid.

Similarly, other users 3-N, the requester 1, the requester 2, thefabrication entity 1, and the fabrication entity 2 provides bids for thedesign represented by the block or the schematic 1830. The royaltygenerator tool 304 receives the various bids and determines which of thebids as the highest. The royalty generator tool 304 sends an acceptanceof the bid that is the highest via the computer network 110 to the usercomputing device 2 for display of the acceptance within the user account2.

FIG. 19A is a diagram of a system 1900 to illustrate functionality ofthe workspace application 180 and storage of various files, such as atestbench netlist file 1902 and the specification file SF1 within thesearchable storage 162. The system 1900 includes the workspaceapplication 180, the searchable storage 162, and the automaticcertification server 112. The requester 1 accesses the workspaceapplication 180 that is executed by the management server 152. Forexample, the requester 1 accesses the website that is controlled by thedesign engineering entity to log into the requester account 1 to furthergain access to the workspace application 180. When the testbenchschematic drawing 1806 is generated, the management server 152 executesthe workspace application 180 to capture various parts, such as theblock, the one or more power sources coupled to one or more input pinsof the block, and the load coupled to an output pin of the block, togenerate a netlist. Moreover, the management server 152 executes theworkspace application 180 to store the netlist within the testbenchnetlist file 1902 and to store the testbench netlist file 1902 withinthe searchable storage 162, such as a cloud storage. Moreover, themanagement server 152 generates the specification file SF1 that includesthe data sheet 1602 and stores the specification file SF1 within thesearchable storage 162.

FIG. 19B is a diagram of an embodiment of the system 1900 to illustratea storage of a circuit netlist file 1920 associated with the schematic1830 in the searchable storage 162. The management server 152 executesthe workspace application 180 to capture the schematic 1830 to generatethe circuit netlist file 1920. For example, a circuit netlist filestores identifies, such as names or model numbers, of components, suchas resistors, capacitors, transistors, logic gates, of the schematic1830 and stores connections between the components. The managementserver 152 stores the circuit netlist file 1920 as a design file withinthe design database 160, of FIG. 1B-2, within the searchable storage162.

FIG. 19C is a diagram of an embodiment of the system 1900 to illustratea simulation of a design of the schematic 1830. The automaticcertification server 112 accesses the testbench netlist file 1902, thespecification file SF1, and the circuit netlist file 1920 from thesearchable storage 162 and executes an automatic certificationgenerator-simulator (gensim) tool 1950 to generate one or moresimulation netlists 1952 for performing one or more simulation tests onthe schematic 1830. The one or more simulation netlists 1952 are storedin one or more simulation files. The automatic certification server 112executes an automatic certification launch tool 1954. Upon execution ofthe automatic certification launch tool 1954, the automaticcertification launch tool 1954 accesses the one or more simulation filesto access the one or more simulation netlists 1952 from the automaticcertification gensim tool 1950 to run simulation tests on the schematic1830. When the simulation tests are run, results 1956 of the simulationtests are generated by the automatic certification launch tool 1954. Theresults 1956 are stored in the data sheet 1602 by the automaticcertification server 112.

When a design is to be accessed by the requester computing devices 1 and2 via corresponding requester accounts 1 and 2 based on a name of thedesign, such as a name of an integrated circuit having the design, themanagement server 152 identifies the data sheet 1602 having the results1956 based on the name. The management server 152 sends the data sheet1602 having the results 1956 via the computer network 110 and therequester accounts 1 and 2 to the requester computing devices 1 and 2for display of the data sheet 1602 on the requester computing devices 1and 2. The requesters 1 and 2 use the requester computing devices 1 and2 to bid on the design based on the results 1956. For example, if theresults 1956 indicate that the design passes the simulation tests, therequester 1 bids a higher amount within a bid amount field displayed onthe requester computing device 1 than if the results 1956 indicate thatthe design fails the simulation tests. The management server 152receives the bids from the requester computing devices 1 and 2 viacorresponding requester accounts 1 and 2 and the computer network 110and compares the bids to determine the highest bid. The managementserver 152 further sends the bids including the highest bid to thedesigner via an account, such as the user account 1. The designer uses acomputing device, such as the user computing device 1, to select, viathe user account 1, an option to indicate acceptance of one of the bids,such as the highest bid, to the management server 152. The managementserver 152 sends via the computer network 110 an indication of theacceptance of one of the bids by the designer to the requester 1 via therequester account 1.

In one embodiment, the automatic certification generator-simulator(gensim) tool 1950 is the same as the circuit design verification tool188.

FIG. 19D is a diagram of an embodiment of the system 1900 to illustratestorage of the results 1956 in the design database 160. The automaticcertification server 112 stores the results 1956 within the designdatabase 160.

It should be noted that in one embodiment, the automatic certificationgensim tool 1950 and the automatic certification launch tool 1954 areparts of the design simulation report generator tool 184 of FIG. 3.Furthermore, it should be noted that in an embodiment, the automaticcertification gensim tool 1950 and the automatic certification launchtool 1954 are parts of the circuit design verification tool 188 of FIG.1F. Moreover, it should be noted that in an embodiment, the automaticcertification gensim tool 1950 and the automatic certification launchtool 1954 are parts of the local test bench tool 165 of FIG. 1F.

FIG. 20A is a diagram of a portion of a data sheet 2000. The data sheet2000 is an example of the data sheet 1602 of FIG. 16. The data sheet2000 includes a design due date for the users 1-N for submitting thedesign to the requester account 1 via respective user accounts 1-N.Moreover, the data sheet 2000 includes a budget for generating a design,testing the design, generating a prototype of the design, and/or testingthe prototype of the design. In addition, the data sheet 2000 andidentifies an owner, such as an intellectual property owner of thedesign. The intellectual property owner has rights, such as patentrights, to the design.

Moreover, the data sheet 2000 includes a name of the design andidentifies a fabrication entity that will generate a prototype based onthe design and/or integrated circuits based on the design. In oneembodiment, a name of a design and a name of a design challenge are usedherein interchangeably. The data sheet 2000 further includes parameters2004, such as names of pins of the design, descriptions of the pins,types of signals carried by the pins, directions of the signals from astandpoint of the pins, minimum voltages at the pins, and maximumvoltages at the pins. Examples of the names of the pins include Vdd,Vss, Vin, Vout, and GND for ground. Examples of the directions of thesignals include input directions and output directions in which signalsare carried by the pins. A signal is received by a pin when the signalis an input signal or is output from the pin when the signal is anoutput signal. Examples of the minimum voltages at a pin include aminimum limit, which is a minimum amount of voltage that is to besupplied to the pin or is to be output from the pin during a test of thedesign and/or a test of a prototype fabricated based on the design.Similarly, examples of the maximum voltages at a pin include a maximumlimit, which is a maximum amount of voltage that is to be supplied tothe pin or is to be output from the pin. The data sheet 2000 furtherincludes the block having some of the pins as pin inputs for receiving asignal and some of the pins as pin outputs for generating a signalduring a test of the design and/or a test of a prototype fabricatedbased on the design.

FIG. 20B is another portion of the data sheet 2000 and is a continuationof the data sheet 2000 of FIG. 20A. Another example of the parameter ofthe specification of the data sheet 200 further includes a typical valueof a resistor, which is used as the load that is coupled to an outputpin of the block to test the block. Yet another example of the parameterof the specification of the data sheet 200 further includes a typicalvalue of a capacitor, which is used as the load that is coupled to anoutput pin of the block to test the block. Additional examples of theparameters of the specification of the data sheet 2000 include atemperature of operation of a prototype generated based on a design ofthe block, a rise time of a voltage at an input pin of the block, and afrequency of operation of the block.

The data sheet 2000 includes different values, such as minimum andmaximum values, of the same parameter for performing different testmethods, such as applying different conditions, on the block. Forexample, one of the test methods includes that a prototype generatedbased on the block represented in the data sheet 2000 operate within atemperature range, such as between a minimum temperature of −40 degreescentigrade (° C.) and a maximum temperature of 125° C. or between aminimum temperature of 20° C. and a maximum temperature of 100° C.,without being damaged. As another example one of the test methodsincludes that an output pin of the block represented in the data sheet2000 operate, such as be able to output a voltage, within a voltagerange while satisfying that other parameters at other pins of the blockremain within limits defined in a specification. An example of thevoltage range includes a voltage between a minimum of 10 volts and amaximum of 50 volts.

As shown in the data sheet 2000, a minimum frequency of operation of theblock or prototype, a maximum frequency of operation of the block orprototype, a rise time of the block or prototype, and a voltage that issupplied to the block or prototype are some examples of processtechnology variants. For example, when the prototype is to be used in tocontrol an etch process in which a semiconductor wafer is being etched,a first frequency of operation and a first voltage of operation of theprototype is different. A voltage of operation of the prototype iscontrolled by the voltage that is supplied to the prototype. The firstfrequency of operation is different compared to a second frequency ofoperation and the first voltage of operation is different from a secondvoltage of operation of the prototype. The prototype has the secondfrequency of operation and the second voltage of operation when theprototype is used to control a deposition process in which materials arebeing deposited on a semiconductor wafer. The temperature range, thevoltage range, and the process technology variants are examples ofglobal testing parameters for operation of the prototype. Moreover, thetemperature range, the voltage range, and the process technologyvariants are examples of electrical parameters of the data sheet 2000.Other examples of the electrical parameters include an amount of powerto be input to or output from the prototype or block, values ofcomponents, such as transistors, resistors, inductors, and capacitors,used within the block or prototype, and a range of frequency ofoperation of the block or prototype, a rise time of the block orprototype.

In one embodiment, an electrical parameter of the block or prototype isa parameter that controls a function, such as an output power or afrequency of operation or an output voltage or an output current or atransfer function, of the block or prototype without affecting a size ofthe block or prototype. Moreover, a physical parameter of the block orprototype is a parameter that affects a size of the block or prototypeand does or does not affect the function of the block or prototype.

FIG. 20C is yet another portion of the data sheet 2000 and is acontinuation of the data sheet 2000 of FIG. 20B. FIG. 20C illustratesdifferent values of the same parameters than those are illustrated inFIG. 20B. For example, FIG. 20C lists different conditions, such asdifferent values of the parameters, to apply to the block, than thoselisted in FIG. 20B. To illustrate, the different conditions include atemperate range at which an integrated circuit, such as the prototype,having the parameters of the data sheet 2000 is to operate or towithstand and a voltage range which the integrated circuit is toreceive. In one embodiment, a different test bench schematic isgenerated by the management server 152 for each of the conditions.

FIG. 20D is another portion of the data sheet 2000 and is a continuationof the data sheet 2000 of FIG. 20C. Physical parameters, such as anarea, or a width, or a height, or a range between a minimum value of thearea and a maximum value of the area, or a range between a minimum valueof the height and a maximum value of the height, or a range between aminimum value of the width and a maximum value of the width, of theprototype of an integrated circuit chip that is generated based on thespecification within the data sheet 2000 are provided in FIG. 20D. Thearea of the prototype, such as an integrated circuit chip, is a productof the width of the prototype and a length of the prototype. The widthof the prototype is perpendicular to the length of the prototype andboth the length and the width are perpendicular to the height of theprototype.

In one embodiment, the data sheet 2000 includes a pass indicator, suchas “P” or “Pass”, or a fail indicator, such as “F” or “Fail”, for eachelectrical parameter on the data sheet 2000. The pass or fail indicatorfor the electrical parameters is generated by the circuit designverification tool 188 of FIG. 1F. For example, the circuit designverification tool 188 couples the power supply to the input pin of theschematic 1830 of FIG. 18C-4, couples a load to the output pin of theschematic 1830, and provides an instantiation value of an electricalparameter to the input pin of the schematic 1830 of FIG. 18C-4 togenerate an output value of the electrical parameter at the output pinof the schematic 1830 to test the schematic 1830. When the output valueis outside a range of values of the electrical parameter provided in thedata sheet 2000, the circuit design verification tool 188 determinesthat the schematic 1830 fails a test, such as a simulation, for theelectrical parameter. On the other hand, when the output value is withinthe range of values of the electrical parameter provided in the datasheet 2000, the circuit design verification tool 188 determines that theschematic 1830 passes the test for the electrical parameter. The circuitdesign verification tool 188 generates the pass indicator upondetermining that the test is passed for the electrical parameter. On theother hand, the circuit design verification tool 188 generates the failindicator upon determining that the test is failed for the electricalparameter. The circuit design verification tool 188 provides the passand fail indicators to the data sheet builder tool 318.

The data sheet builder tool 318 updates the data sheet 2000 with thepass and fail indicators. For example, in a row of the data sheet 2000that has a first electrical parameter, the data sheet builder tool 318aligns the pass indicator or the fail indicator for the first electricalparameter in the row. Moreover, in a row of the data sheet 2000 that hasa second electrical parameter, the data sheet builder tool 318 alignsthe pass indicator or the fail indicator for the second electricalparameter in the row. As another example, the data sheet builder tool318 incorporates into the data sheet 2000, a correspondence between theelectrical parameters and the pass and fail indicators for theelectrical parameters as a separate table. To illustrate, the data sheet2000 is updated by the data sheet builder tool 318 to include a tablethat has a first row that lists an output voltage as an electricalparameter and the pass or fail indicator. The data sheet 2000 is updatedby the data sheet builder tool 318 to include in the table a second rowthat lists an output current as an electrical parameter and the pass orfail indicator.

In an embodiment, the data sheet 2000 includes a score for eachelectrical parameter on the data sheet 2000. The score for theelectrical parameters is generated by the circuit design verificationtool 188. For example, the circuit design verification tool 188 couplesthe power supply to the input pin of the schematic 1830 of FIG. 18C-4,couples a load to the output pin of the schematic 1830, and provides aninstantiation value of an electrical parameter to the input pin of theschematic 1830 of FIG. 18C-4 to generate an output value of theelectrical parameter at the output pin of the schematic 1830 to test theschematic 1830. When the output value is outside a range of values ofthe electrical parameter provided in the data sheet 2000 by apre-determined limit, the circuit design verification tool 188 generatesa first score indicating that the schematic 1830 fails a test for theelectrical parameter. On the other hand, when the output value is withinthe range of values of the electrical parameter provided in the datasheet 2000, the circuit design verification tool 188 generates a secondscore indicating that the schematic 1830 passes the test for theelectrical parameter. When the output value is outside the range ofvalues of the electrical parameter provided in the data sheet 2000 butwithin the pre-determined limit, the circuit design verification tool188 generates a third score indicating that the schematic 1830 has ahigher quality than another schematic for which the first score isgenerated and indicating that the schematic 1830 has a lower qualitythan another schematic for which the second score is generated. Thecircuit design verification tool 188 provides the score, such as thefirst, second, or third score, to the data sheet builder tool 318.

The data sheet builder tool 318 updates the data sheet 2000 with thescore. For example, in a row of the data sheet 2000 that has a firstelectrical parameter, the data sheet builder tool 318 aligns a score forthe first electrical parameter in the row. Moreover, in a row of thedata sheet 2000 that has a second electrical parameter, the data sheetbuilder tool 318 aligns a score for the second electrical parameter inthe row. As another example, the data sheet builder tool 318incorporates into the data sheet 2000, a correspondence between theelectrical parameters and the scores for the electrical parameters as aseparate table. To illustrate, the data sheet 2000 is updated by thedata sheet builder tool 318 to include a table that has a first row thatlists an output voltage as an electrical parameter and the scoregenerated by testing the first electrical parameter. The data sheet 2000is updated by the data sheet builder tool 318 to include in the table asecond row that lists an output current as an electrical parameter andthe score generated by testing the second electrical parameter.

In one embodiment, the data sheet 2000 includes a pass indicator, suchas “P” or “Pass”, or a fail indicator, such as “F” or “Fail”, for eachphysical parameter on the data sheet 2000. The pass or fail indicatorfor the physical parameters is generated by the layout designverification tool 190 of FIG. 1F. For example, the layout designverification tool 190 determines whether a value of a physicalparameter, of an integrated circuit, received from the user N via theuser account N and the user computing device N via the computer network110 is within a range of values of the physical parameter provided inthe data sheet 2000. When the received value of the physical parameteris outside the range of values of the physical parameter provided in thedata sheet 2000, the layout design verification tool 190 determines thata layout design generated based on the schematic 1830 fails a test forthe physical parameter. On the other hand, when the received value ofthe physical parameter is within the range of values of the physicalparameter provided in the data sheet 2000, the layout designverification tool 190 determines that the layout design passes the testfor the physical parameter. The layout design verification tool 190generates the pass indicator upon determining that the test is passedfor the physical parameter. On the other hand, the layout designverification tool 190 generates the fail indicator upon determining thatthe test is failed for the physical parameter. The layout designverification tool 190 provides the pass and fail indicators to the datasheet builder tool 318.

The data sheet builder tool 318 updates the data sheet 2000 with thepass and fail indicators. For example, in a row of the data sheet 2000that has a first physical parameter, the data sheet builder tool 318aligns the pass indicator or the fail indicator for the first physicalparameter in the row. Moreover, in a row of the data sheet 2000 that hasa second physical parameter, the data sheet builder tool 318 aligns thepass indicator or the fail indicator for the second physical parameterin the row. As another example, the data sheet builder tool 318incorporates into the data sheet 2000, a correspondence between thephysical parameters and the pass and feel indicators for the physicalparameters as a separate table. To illustrate, the data sheet 2000 isupdated by the data sheet builder tool 318 to include a table that has afirst row that lists a width of a transistor as a physical parameter andthe pass or fail indicator. The data sheet 2000 is updated by the datasheet builder tool 318 to include in the table a second row that lists alength of the transistor as another physical parameter and the pass orfail indicator.

In an embodiment, the data sheet 2000 includes a score for each physicalparameter on the data sheet 2000. The score for the physical parametersis generated by the layout design verification tool 190. For example,the layout design verification tool 190 determines whether a value of aphysical parameter, of an integrated circuit, received from the user Nvia the user account N and the user computing device N via the computernetwork 110 is outside a range of values of the physical parameterprovided in the data sheet 2000 by a pre-set limit. Upon determiningthat the received value of the physical parameter is outside the rangeof values of the physical parameter by the pre-set limit, the layoutdesign verification tool 190 generates a first score indicating that alayout design generated based on the schematic 1830 fails a test for thephysical parameter. On the other hand, when the received value of thephysical parameter is within the range of values of the physicalparameter provided in the data sheet 2000, the layout designverification tool 190 generates a second score indicating that thelayout design passes the test for the electrical parameter. When thereceived value of the physical parameter is outside the range of valuesof the physical parameter provided in the data sheet 2000 but within thepre-set limit, the layout design verification tool 190 generates a thirdscore indicating that the layout design has a higher quality thananother layout design for which the first score is generated and has alower quality than another layout design for which the second score isgenerated. The layout design verification tool 190 provides the score,such as the first, second, or third score, to the data sheet buildertool 318.

The data sheet builder tool 318 updates the data sheet 2000 with thescore. For example, in a row of the data sheet 2000 that has a firstphysical parameter, the data sheet builder tool 318 aligns the score forthe first physical parameter in the row. Moreover, in a row of the datasheet 2000 that has a second physical parameter, the data sheet buildertool 318 aligns the score for the second physical parameter in the row.As another example, the data sheet builder tool 318 incorporates intothe data sheet 2000, a correspondence between the physical parametersand the scores for the physical parameters as a separate table. Toillustrate, the data sheet 2000 is updated by the data sheet buildertool 318 to include a table that has a first row that lists a width of atransistor as a physical parameter and the score for the physicalparameter. The data sheet 2000 is updated by the data sheet builder tool318 to include in the table a second row that lists a length of thetransistor as another physical parameter and the score for the otherphysical parameter.

In one embodiment, the layout design verification tool 190 generates acomposite pass indicator, such as “P” or “Pass”, or a composite failindicator, such as “F” or “Fail”, for all the parameters of the datasheet 2000 based on a pass indicator or a fail indicator for each of theparameters. For example, the layout design verification tool 190determines that a majority of the parameters of the data sheet 2000 havea pass indicator to further determine that a design of an integratedcircuit to be fabricated from the parameters of the data sheet 2000 hasa composite pass indicator. On the other hand, the layout designverification tool 190 determines that a majority of the parameters ofthe data sheet 2000 have a fail indicator to further determine that adesign of an integrated circuit to be fabricated from the parameters ofthe data sheet 2000 has a composite fail indicator. As another example,the layout design verification tool 190 determines from weights assignedto the parameters of the data sheet 2000 and pass or fail indicators ofthe parameters a composite pass or a composite fail indicator for thedata sheet 2000. To illustrate, when two out of three parameters of thedata sheet 2000 have fail indicators and the third parameter has a passindicator, the layout design verification tool 190 determines that thethird parameter has a higher weight than weights of the first and secondparameters and assigns a composite pass indicator to the data sheet2000. The layout design verification tool 190 sends the composite passor the composite fail indicator to the data sheet builder tool 318. Thedata sheet builder tool 318 incorporates the composite pass indicator orthe composite fail indicator into the data sheet 2000. For example, thedata sheet builder tool 318 includes within the data sheet 2000 thecomposite pass indicator or the composite fail indicator on a webpagehaving the data sheet 2000.

In an embodiment, the layout design verification tool 190 generates acomposite score for all the parameters of the data sheet 2000 based onindividual scores of each of the parameters. The composite score isgenerated to determine whether a design of an integrated circuit to befabricated from the parameters of the data sheet 2000 passes or fails atest. For example, the layout design verification tool 190 calculates aweighted average of the scores of the parameters of the data sheet togenerate a composite score. To illustrate, the layout designverification tool 190 assigns a greater weight to a parameter of thedata sheet 2000 than to another parameter of the data sheet 2000. Aweight to be assigned to a parameter is stored in the searchable storage162 by the management server 152. As another illustration, the layoutdesign verification tool 190 assigns the same weight to all parametersof the data sheet 2000. Upon determining that the weighted average isoutside a pre-determined range of averages, the layout designverification tool 190 determines that the design passes the test. On theother hand, upon determining that the weighted average is within thepre-determined range of averages, the layout design verification tooldetermines that the design fails the test. As another example, thelayout design verification tool 190 calculates a weighted average of thescores of the parameters of the data sheet 2000. The weighted average isan example of a composite score. Upon determining that the compositescore is greater than a predetermined average, the layout designverification tool 190 determines that the design passes the test. On theother hand, upon determining that the composite score is less than thepre-determined average, the layout design verification tool determinesthat the design fails the test. The layout design verification tool 190sends the composite score to the data sheet builder tool 318. The datasheet builder tool 318 incorporates the composite score into the datasheet 2000. For example, the data sheet builder tool 318 includes withinthe data sheet 2000 the composite score on a webpage having the datasheet 2000.

In one embodiment, in addition to the composite score, the compositepass indicator of the composite fail indicator is included within thedata sheet 2000 by the data sheet builder tool 318. In an embodiment,instead of the average values of scores of the parameters of the datasheet 2000, a median value of the scores is calculated by the layoutdesign verification tool 190 to generate a composite score for the datasheet 2000.

In an embodiment, the design competition generator tool 310 of FIG. 3compares the composite indicators, such as a composite pass indicator ora composite fail indicator, of two different data sheets to determine awinner of a competition for generating a design of an integratedcircuit. For example, the design competition generator tool 310 comparesa first composite indictor from a first data sheet, such as the datasheet 2000, and a second composite indictor from a second data sheet,and determines whether the first composite indictor is pass and thesecond composite indicator is fail. Upon determining that the firstcomposite indictor is pass and the second composite indicator is fail,the design competition generator tool 310 determines that the useraccount 1 that is accessed to generate a first design of the integratedcircuit is a winner of the competition and the user account 2 that isaccessed to generate a second design of the integrated circuit is notthe winner. On the other hand, upon determining that the secondcomposite indictor is pass and the first composite indicator is fail,the design competition generator tool 310 determines that the useraccount 2 that is accessed to generate the second design of theintegrated circuit is a winner of the competition and the user account 1that is accessed to generate the first design of the integrated circuitis not the winner. The first design is assigned the first compositeindicator and the second design is assigned the second compositeindicator by the layout design verification tool 190, and both the firstcomposite indicator and the second composite indicator are obtained bythe design competition generator tool 310 from the searchable storage162 or from the layout design verification tool 190. Both the first andsecond data sheets have the same minimum and maximum limits of theelectrical parameters and the same minimum and maximum limits of thephysical parameters. For example, both the first and second data sheetshave minimum and maximum values of parameters based on which the designsfor the integrated circuit are generated by the users 1 and 2 via thecorresponding user accounts 1 and 2. The user 1 accesses the first datasheet having the first composite indicator via the user account 1 andthe computer network 110 from the data sheet builder tool 318. Moreover,the user 2 accesses the second data sheet having the second compositeindicator via the user account 2 and the computer network 110 from thedata sheet builder tool 318.

In an embodiment, the design competition generator tool 310 of FIG. 3compares the composite scores of two different data sheets to determinea winner of a competition for generating a design of an integratedcircuit. For example, the design competition generator tool 310 comparesa first composite score from a first data sheet, such as the data sheet2000, and a second composite score from a second data sheet, anddetermines whether the first composite score is greater than the secondcomposite score. Upon determining that the first composite scoresgreater than the second composite score, the design competitiongenerator tool 310 determines that the user account 1 that is accessedto generate a first design of the integrated circuit is a winner of thecompetition and the user account 2 that is accessed to generate a seconddesign of the integrated circuit is not the winner. The first design isassigned the first composite score and the second design is assigned thesecond composite score by the layout design verification tool 190. Asexplained above, both the first and second data sheets have the sameminimum and maximum limits of the electrical parameters and the sameminimum and maximum limits of the physical parameters.

FIG. 20E is a diagram of an embodiment of a data sheet 2010 toillustrate pass (P) or fail (F) evaluations for each parameter of thedata sheet 2010 and a composite pass/fail evaluation for all theparameters of the data sheet 2010. FIG. 20F is a continuation of thedata sheet 2010 of FIG. 20E. FIG. 20G is a continuation of the datasheet 2010 of FIG. 20F. FIG. 20H is a continuation of the data sheet2010 of FIG. 20G.

FIG. 20I is a diagram of an embodiment of a data sheet 2020 toillustrate scores assigned to each parameter of the data sheet 2020 anda composite score for all the parameters of the data sheet 2020. FIG.20J is a continuation of the data sheet 2020 of FIG. 20I. FIG. 20K is acontinuation of the data sheet 2020 of FIG. 20J. FIG. 20L is acontinuation of the data sheet 2020 of FIG. 20K.

FIG. 21 is a diagram to illustrate a variety of integrated circuit chipsthat are designed using the online design engineering system 102. Forexample, the online design engineering system 102 is used to generate adesign of a design regulator, a power manager switch, a chip thatimplements a wireless protocol, a chip that implements a wired protocol,a filter, a sensor, and a driver circuit.

FIG. 22 is an embodiment of a computing device 2200 that is used toexecute the design engineering methods described herein. In oneembodiment, the computing device 2200 is an example of any of thecomputing devices, such as any of the user computing devices 1-N, therequester computing device 1, the requester computing device 2, thefabrication computing device 1, or the fabrication computing device 2,described herein. The computing device 2200 may include more or lesscomponents than those shown in FIG. 22.

The computing device 2200 includes a processor 2235 in communicationwith a memory device 2202 via a bus 2240. The processor 2235 performsthe functions described herein as being performed by a computing device,described herein. The processor 2235 is also in communication with amain memory device 2203 via the bus 2240. The computing device 2200includes a network interface controller 2242, an input device 2236, andan input/output (I/O) interface 2234. Examples of a network interfacecontroller include a network interface card and a network adapter thatapply a communication protocol, such as a Transmission Control Protocolover Internet protocol (TCP/IP) to communicate with the computer network110. In one embodiment, instead of a network interface controller, amodem is used to communicate with the computer network 110. The networkinterface controller 2242 includes circuitry for coupling the computingdevice 2200 to the computer network 110.

The input device 2236 is coupled with the bus 2240 via the input/outputinterface 2234. Examples of the input device 2236 include a keyboard, akeypad, a touch screen, a mouse, and/or one or more buttons that areused to power-up and boot the computing device 2200. In an embodiment,the input/output interface 2234 converts a signal received from theinput device 2236 into a signal that is compatible with the bus 2240. Inone embodiment, the input/output interface 2234 converts the signal thatis received via the bus 2240 to the signal that is sent to the inputdevice 2236.

In an embodiment, the computing device 2200 includes a set of speakers(not shown) that are coupled to the bus 2240 via an audio interface (notshown). The audio interface performs a variety of audio-relatedprocesses, such as accessing the audio data from the memory device 2233and filtering the audio data. Moreover, in one embodiment, the computingdevice includes a display device (not shown), such as, for example, aliquid crystal display device, a light emitting diode display device, aplasma display, or a cathode ray tube display for displaying a userinterface.

The memory device 2233 includes a random-access memory (RAM), aread-only memory (ROM), or a combination thereof. The memory device 2233illustrates an example of computer storage media for storage ofinformation, such as, computer-readable instructions, data structures,program modules or other data. The memory device 2233 stores a basicinput/output system (“BIOS”) for controlling low-level operation of thecomputing device 2200. The main memory device 2233 also stores anoperating system for controlling the operation of computing device 2200.It will be appreciated that in one embodiment, the operating systemincludes UNIX™, LINUX™, or Windows™ operating system.

It should be noted that although one processor 2235 is shown within thecomputing device 2200, in one embodiment, a different number ofprocessors, such as two or more, etc., are included within the computingdevice 2200 and the different number of processors perform theoperations described in the present disclosure as being performed by acomputing device. Also, it should be noted that in one embodiment, morethan two memory devices store data that is stored in the memory device2233.

FIG. 23 is a diagram of an embodiment of a server 2300 described herein.The server 2300 is an example of the management server 152 or of theautomatic certification server 112 or of any other server describedherein. The server 2300 includes a CPU 2302, a ROM 2304, a RAM 2306, ahard disk drive (HD) or storage memory 2308, and input/output (I/O)interface 2310 for coupling input/output devices, such as, a keyboard,monitor, printer, electronic pointing device (e.g., mouse, trackball,stylus, etc.), or the like. In one embodiment, the ROM 2304 and/or RAM2306 includes one or more databases, described herein. It should benoted that in an embodiment, the server 2300 has more than one CPU, ROM,RAM, HD, I/O, or other hardware components.

In an embodiment, multiple designers create a circuit design and areconsidered joint owners of the circuit design by the online designengineering system 102. The online design engineering system 102 keeps arecord of a user account that is used to generate a design, and therecord is then accessed to determine that a user assigned the useraccount is an owner of the circuit design. In an embodiment in whichmultiple user accounts are used to generate circuit designs, the usersassigned the user accounts are considered owners of the circuit design.

Moreover, in one embodiment, the online design engineering system 102provides an iterative process with which to measure success or failureof a circuit design in a shorter amount of time than that provided byconventional prototype development systems. For example, the onlinedesign engineering system 102 is accessed by the users 1 through N viathe respective user accounts 1-N to create and submit designs to theonline design engineering system 102. Simulation software providedwithin the online design engineering system 102 is executed to run asimulation on the circuit designs. The one or more fabrication entitiesfabricate one or more prototypes based the designs. The one or moreprototypes are tested using the online design engineering system 102,e.g., the one or more prototypes are tested on the PCB by using softwarethat is stored in the online design engineering system 102. As such,there is no need for the users 1 through N to have one-to-onerelationships or personal contacts with the fabrications entities orwith the requester. Rather, the online design engineering system 102facilitates generation and execution of simulations of designs forfabricating prototypes and testing the prototypes. The online designengineering system 102 allows for a higher number of iterations ofdesigns and of the prototypes compared to the conventional prototypedevelopment systems.

FIG. 24 is a diagram of an embodiment of a system 2400 to illustratethat there is no non-disclosure agreement (NDA) between fabricationentities, such as the fabrication entity 1 and fabrication entity 2, andthe community. Layout features that are used to generate a layout designare not visible to one or more users, such as the users 1 through N, ofthe community. Examples of the layout features include n-wells, p-wells,n-type diffusions, p-type diffusions, n-type ion implantations, p-typeion implantations, p-type substrates, n-type substrates, contacts,metals, vias, polysilicons, oxide cuts, etc. The layout features of thelayout design are created by a fabrication entity. A fabricationcomputing device, such as the fabrication computing device 1, providesaccess to the layout features, which are unobfuscated, to the obfuscatortool 182 via the computer network 110. The layout features are accessedby the obfuscator tool 182 and are obfuscated by the obfuscator tool182. The obfuscation of the layout features protects intellectualproperty of the fabrication entities and no NDA is needed between thefabrication entities and the community of users.

FIG. 25 is a diagram of an embodiment of a system 2500 to illustratethat a user uses a layout design of an integrated circuit chip withanother layout design of another integrated circuit chip or with anintegration circuit design, such as glue logic, to create yet anotherintegrated circuit chip design. The user 1 operates the user computingdevice 1 to access the website that is controlled by the designengineering entity. The user 1 logs into the user account 1 via thewebsite and selects a try before buy option, such as a try before buybutton, displayed on a webpage accessible via the website. The user 1further operates the user computing device 1 to access the workspaceapplication 180 to access the layout design tool 166. Upon receiving theselection of the try before buy option, the management server 152provides access to an obfuscated layout design 2502. For example, theobfuscated layout design 2502 is sent from the design database 160 viathe computer network 110 to the user computing device 1 via the useraccount 1 and the workspace application 180 for display on the displaydevice of the user computing device 1. The obfuscated layout design 2502has one or more input ports, such as an input port 2504A, and one ormore output ports, such as an output port 2504B, and has the obfuscatedlayout features that are generated by the obfuscator tool 182. Theobfuscated layout features are generated by obfuscating the layoutfeatures that are accessed from the fabrication computing device 1 viathe computing network 110. The obfuscated layout design 2502 isdisplayed as an opaque object, such as a black box, or a colored box, ora colored object of any shape, in which the layout features areobfuscated. The obfuscated layout design 2502 is sent from theobfuscator tool 182 via the computer network 110 to the user computingdevice 1 for display on the display device of the user computing device1.

The user 1 couples the obfuscated layout design 2502 with a layoutdesign that is generated by the user 1 via the user account 1 byaccessing the layout design tool 166. For example, the user 1 couples aninput port of the layout design generated by the user 1 with the outputport 2504B and couples the output port of the layout design generated bythe user 1 with the input port 2504A to generate an integrated circuitchip design. The user 1 selects a test button displayed on the displaydevice of the user computing device 1 to execute the local layoutverification tool 167 or the layout design verification tool 190 of FIG.1F to simulate the integrated circuit chip design. The integratedcircuit chip design includes the layout design generated by the user 1and the obfuscated layout design 2502. There is no NDA needed between afabrication entity that creates the layout features that are hidden inthe obfuscated layout design 2502 and the user 1 because the user 1cannot access the layout features via the user account 1.

FIG. 26A is a diagram of an embodiment to illustrate generation ofobfuscated designs, such as an obfuscated design 2604A and 2604B, from aschematic 2602. Each obfuscated design 2604A and 2604B is an example ofa generic layout feature representation. For example, the obfuscateddesign 2604A does not show that the transistor T1 has a gate, a drain,and a source. Similarly, the obfuscated design 2604B does not show thatthe transistor T2 has a gate, a drain, and a source.

The transistor T1 is represented by the obfuscator tool 182 as theobfuscated design 2604A. Similarly, the transistor T2 is represented bythe obfuscator tool 182 as the obfuscated design 2604B.

An obfuscated design of a component, such as a transistor or a logicgate, of a schematic has the same electrical characteristics as that ofthe component. For example, the obfuscated design 2604A has the samerise time or the same threshold voltage or the same transfercharacteristic or the same output characteristic as that of thetransistor T1. As another example, the obfuscated design 2604B has thesame rise time or the same threshold voltage or the same transfercharacteristic or the same output characteristic as that of thetransistor T2. Other examples of the electrical characteristics includea current gain of a bipolar junction transistor, or power consumption ofa logic gate, or a speed with which data is processed by the logic gate.

The user 1 accesses the workspace application 180 via the user account 1on the user computing device 1. Upon accessing the workspace application180, the user 1 uses the user computing device 1 to access the circuitdesign tool 164 to generate the schematic 2602 on a workspace display2603. The workspace display 2603 includes an image of the schematic 2602displayed on the display device of the user computing device 1. Theschematic 2602 includes a p-type metal oxide semiconductor field effecttransistor (MOSFET) T1 and an n-type MOSFET T2. A source of thetransistor T1 is coupled to a voltage source, such as a 5 volt voltagesource, and a source of the transistor T2 is coupled to a voltagepotential, such as a ground voltage potential. Moreover, gates of boththe transistors T1 and T2 are coupled with each other as an inputconnection, which for example, is coupled to a power source. The inputconnection is labeled as “in” in FIG. 26A. Also, a drain of thetransistor T1 and a drain of the transistor T2 is coupled to an outputconnection. The output connection is labeled as “out” in FIG. 26A. Thegate of the transistor T1 is connected to the gate of the transistor T2via a connection CN1, which is coupled to the input connection. Also,the drain of the transistor T1 is connected to the drain of thetransistor T2 via a connection CN2, which is coupled to the outputconnection.

The user 1 uses the user computing device 1, the workspace application180, and the circuit design tool 164 to select a size of the transistorT1, such as a width of the transistor T1 and a length of the transistorT1, and to select a number of transistors T1 to be used in the schematic2602. Moreover, the user 1 uses the user computing device 1, theworkspace application 180, and the circuit design tool 164 to select asize of the transistor T2, such as a width of the transistor T2 and alength of the transistor T2, and to select a number of transistors T2 tobe used in the schematic 2602.

When a selection of an option, such as a save button or a send button,displayed via the user account 1 on the workspace display 2603 is madeby the user 1 via the input device of the user computing device 1, theschematic 2602 is sent via the computer network 110 to the circuitdesign tool 164 of the design engineering system 102. To illustrate, theuser computing device 1 applies the communication protocol to generatepackets from the schematic 2602 and sends the packets via the computernetwork 110 to the design engineering system 102. Upon receiving thepackets, the design engineering system 102 depacketizes the packets toextract the schematic 2602. Also, the management server 152 of thedesign engineering system 102 generates a design file having theschematic 2602 and stores the design file in the design database 160.

The obfuscator tool 182 of the design engineering system 102 accessesthe design file having the schematic 2602 from the design database 160and obfuscates layout features of components, such as the transistors T1and T2, to generate the obfuscated designs 2604A and 2604B. For example,the obfuscator tool 182 renders as opaque the layout features of thetransistor T1 to generate the obfuscated design 2604A and renders asopaque the layout features of the transistor T2 to generate theobfuscated design 2604B. Examples of the layout features of a transistorinclude the transistor and the connections CN1 and CN2. Other examplesof the layout features include a diffusion or a substrate or a well of atransistor.

Moreover, the obfuscator tool 182 excludes scaled representations of thelayout features in the obfuscated designs 2604A and 2604B. For example,the obfuscator tool 182 hides or renders as opaque the scaledrepresentations. A width of a transistor and a length of a transistorare examples of scaled representations of the transistor. Other examplesof scaled representations of a layout feature include a size, such as adepth, or a width, or a length, or a dimension, or a combinationthereof, of the layout feature.

The obfuscated design 2604A includes an input port 2606A and an outputport 2606B. For example, the input port 2606A represents a connection toa gate of the transistor T1 and the output port 2606B represents aconnection to a drain of the transistor T1. Similarly, the obfuscateddesign 2606B includes an input port 2606C and an output port 2606D. Asan example, the input port 2606C represents a connection to a gate ofthe transistor T2 and the output port 2606D represents a connection to adrain of the transistor T2.

The user 1 accesses the workspace application 180 to further access thelayout design tool 166 to generate a layout design from the schematic2602. When the layout design tool 166 is accessed via the user account 1and the computer network 110, the obfuscator tool 182 does not permitthe user 1 via the user account 1 to access the layout features of thetransistors T1 and T2 and generates the obfuscated designs 2606A and2606B. For example, the obfuscator tool 182 does not permit the user 1to access via the user account 1 to select or change spacing betweenwells of the transistors T1 and T2, sizes of the wells, sizes ofsubstrates of the transistors T1 and T2, sizes of contacts of thetransistors T1 and T2, sizes of vias that are coupled to the transistorsT1 and T2, sizes of metals that are coupled to the transistors T1 andT2, sizes of oxide layers of the transistors T1 and T2, sizes ofdiffusions of the transistors T1 and T2, sizes of ion implantations ofthe transistors T1 and T2, types of the transistors T1 and T2, and sizesof polysilicons of the transistors T1 and T2. An example of a size, asused herein, of a layout feature includes a width or a length or a depthor a combination thereof of the layout feature. The layout features arean intellectual property of one or more fabrication entities, such asthe fabrication entity 1 and the fabrication entity 2. Without an NDA,the intellectual property of the fabrication entities is protected whilethe user account 1 is still provided access to the obfuscated designs2604A and 2604B. The obfuscated designs 2604A and 2604B are sent by theobfuscator tool 182 via the computer network 110 and the user account 1to the user computing device 1 for display on the display device of theuser computing device 1.

It should be noted that in an embodiment, although the obfuscateddesigns 2604A and 2604B are generate from different types of transistorsT1 and T2, both the obfuscated designs 2604A and 2604B have the samerepresentation. For example, there is no difference between sizes andshapes of the obfuscated designs 2604A and 2604B. As another example,there is no difference in a number of ports of the obfuscated designs2604A and 2604B.

FIG. 26B is a diagram of an embodiment of a workspace display 2610 toillustrate a manual placement of obfuscated designs and of generatingmanual routes between the obfuscated designs. The workspace display 2610is generated when the user 1 operates the user computing device 1 toaccess the workspace application 180 to further access the layout designtool 166 to generate a layout design from the schematic 2602 of FIG.26A. Upon accessing the layout design tool 166, the user 1 accesses theobfuscated designs 2604A and 2604B from the design database 160 via theuser account 1 and the obfuscator tool 182, and uses the input device ofthe user computing device 1 to place the obfuscated designs 2604A and2604B at positions P1 and P2. For example, the obfuscated design 2604Ais placed at the position P1 and the obfuscated design 2604B is placedat the position P2. As another example, the obfuscated design 2604A isplaced at a position P3 and the obfuscated design 2604B is placed at aposition P4.

Moreover, upon placing the obfuscated designs 2604A and 2604B, the user1 uses the input device of the user computing device 1 to generateroutes, such as metal connections, between the obfuscated designs 2606Aand 2606B to create an integrated circuit chip design 2608, which is alayout design. For example, the user 1 uses the input device of the usercomputing device 1 to access and place a route 2612 between the inputports 2606A and 2606C and to generate a master input port 2620A, whichis connected to the route 2604A. As another example, the user 1 uses theinput device of the user computing device 1 to access and place a route2622 between the output ports 2606B and 2606D and to generate a masteroutput port 2620B, which is connected to the route 2622. The user 1 usesthe input device of the user computing device 1 to connect the masterinput port 2620A to the route 2612 and to connect the master output port2620B to the route 2622. As yet another example, the user 1 uses theinput device of the user computing device 1 to generate a metalconnection between two layout features of a layout design. Theintegrated circuit chip design 2608 includes the master input port 2620Aand the master output port 2620B. Moreover, the user 1 uses the usercomputing device 1 to generate master ports 2620C and 2620D within theintegrated circuit chip design 2608.

Once the obfuscated designs 2604A and 2604B of the integrated circuitchip design 2608 are placed and are connected with each other by theuser 1 via the user computing device 1 and the user account 1, and theuser 1 selects a save option or a send option displayed on the workspacedisplay 2610, the management server 152 generates an outer boundary 2626of the integrated circuit chip design 2608 and the user computing device1 sends the integrated circuit chip design 2608 via the computer network110 to the design engineering system 102. The management server 152generates a design file having the integrated circuit chip design 2608and stores the design file in the design database 160.

FIG. 27 is a diagram of an embodiment of a system 2700 to illustrate anapplication of the obfuscator tool 182 to a process design kit (PDK)that is controlled by the fabrication entity 1. In an embodiment, thefabrication entity PDK is a set of files used within a semiconductorindustry to model a fabrication process for a layout design tool used togenerate a layout design of an integrated circuit. In one embodiment,the fabrication entity PDK is an example of a layout design tool that iscontrolled by the fabrication entity 1. For example, the fabricationentity 1 has licensing rights to use or allow use of the fabricationentity PDK or has intellectual property rights to the fabrication entityPDK. As another example, the fabrication entity PDK is created by thefabrication entity 1 defining a certain technology variation for itsprocesses. The fabrication entity PDK includes a simulation computersoftware, such as a computer program, for verifying a layout design or acircuit design. For example, the fabrication entity PDK includes SPICE™or a modification of SPICE™.

The management server 152 obtains a copy of the fabrication entity PDKvia the computer network 110 from the fabrication entity computingdevice 1. For example, the design engineering entity is provided alicense to use and modify the fabrication entity PDK. As anotherexample, the management server 152 downloads a copy of the fabricationentity PDK from the fabrication computing device 1 via the computernetwork 110 and the fabrication entity account 1. As yet anotherexample, the design engineering entity uses an input device coupled tothe management server 152 to download a copy of the PDK.

The design engineering entity, such as an employee of the designengineering entity, uses the input device coupled to the managementserver 152 and the management server 152 to modify the fabricationentity PDK to generate a DES PDK. For example, the design engineeringentity uses the input device coupled to the management server 152 andthe management server 152 to modify the fabrication entity PDK togenerate the DES PDK. As another example, the fabrication entity PDK isintegrated with the obfuscator tool 182 to generate the DES PDK. Asanother example, the fabrication entity PDK is modified to include callfunctions to the obfuscator tool 182. As yet another example, SPICE™ orits modification is changed to create a verification software tool or isreplaced with another verification software tool, such as Nextgeneration SPICE™ (Ngspice™). To illustrate, SPICE™ or its derivative ismodified by the design engineering entity to create the verificationsoftware tool or is replaced by the design engineering entity withanother verification software tool.

When the layout design tool 166, such as the DES PDK, is accessed viathe computer network 110 by the user computing device N to generate alayout design, the obfuscator tool 182 that is integrated within the DESPDK obfuscates, such as hides, or renders opaque, or covers, layoutfeatures of a component, such as a transistor, a logic gate, a resistor,a capacitor, an inductor, or another electrical element, of a circuitdesign that is generated by the user 1 via the user account 1, togenerate the obfuscated design 2502. For example, when the user Nrequests via the layout design tool 166 an access to the transistor T1or T2, the obfuscated design 2502 is generated from the transistor T1 orthe transistor T2 by obfuscating one or more layout features of thetransistor, and sent from the obfuscator tool 182 via the computernetwork 110 and the user account N to the user computing device N fordisplay of the obfuscated design 2502 on the display device of the usercomputing device N. Each obfuscated design 2604A and 2604B of FIG. 26Ais an example of the obfuscated design 2502.

The user N uses the user computing device N to access the verificationsoftware tool of the DES PDK via the account and the computer network110 to test the obfuscated design 2502. For example, a power source2704, such as a current supply or a voltage supply, is coupled to theinput port 2504A of the obfuscated design 2502 by the verificationsoftware tool of the DES PDK to generate data at the output port 2504Bof the obfuscated design 2702. Examples of the data at the output port2504B include a plot of current I at the output port 2504B versus timet.

In one embodiment, the user N uses the user computing device N to accessthe verification software tool of the DES PDK via the user account N toaccess the integrated circuit chip design 2608 of FIG. 26B from thedesign database 160 and to test the integrated circuit chip design 2608.The verification software tool of the DES PDK is accessed when the userN operates the user computing device N to access the workspaceapplication 180 to further access the verification software tool of theDES PDK. As an example, during the test of the integrated circuit chipdesign 2608, the power source 2704 is coupled to the master input port2620A of the integrated circuit chip design 2608 to generate data at themaster output port 2620B of the integrated circuit chip design 2608.Examples of the data at the master output port 2620B include a plot ofvoltage at the master output port 2620B versus voltage at the masterinput port 2620A. It should be noted that when the integrated circuitchip design 2608 is accessed via the user account N and the verificationsoftware tool of the DES PDK to be tested, there is no display of theschematic 2602 of FIG. 26A based on which the integrated circuit chipdesign 2608 is generated. Electrical characteristics, such as transfercharacteristics or output characteristics or voltage at output versusvoltage at input or current at output versus current at input, of boththe schematic 2602 and the integrated circuit chip design 2608 are thesame. Moreover, when the integrated circuit chip design 2608 is accessedby the user N via the user account N and the verification software toolof the DES PDK to test the integrated circuit chip design 2608, there isno display of one or more of the layout features of the integratedcircuit chip design 2608 and/or of one or more scaled representations ofthe one or more features. Also, when the integrated circuit chip design2608 is accessed by the user N via the user account N and theverification software tool of the DES PDK to test the integrated circuitchip design 2608, a number of components, such as the transistors T1 andT2, are obfuscated by the obfuscator tool 182. To illustrate, when thecomponents are obfuscated, there is no representation of how many of thecomponents are used, positions of the components in the integratedcircuit chip design 2608, types of the components, spacing, such as aperpendicular distance, between two adjacent components in theintegrated circuit chip design 2608, and identities of the components.In the illustration, a type of a component, such as n-type or p-type,identifies the component and/or a series of alphanumeric characters,such as a serial number, assigned to the component identifies thecomponent.

In the embodiment, the obfuscator tool 182 obfuscates the one or morelayout features and/or the one or more scaled representations togenerate a display the integrated circuit chip design 2608 on thedisplay device of the user computing device N via the computer network110 to facilitate a test of the integrated circuit chip design 2608. Forexample, the obfuscator tool 182 obfuscates the routes 2612 and 2622shown in FIG. 26B but does not obfuscate the master input ports 2620Aand 2620B of the integrated circuit chip design 2608. Moreover, theobfuscator tool 182 obfuscates the obfuscated designs 2604A and 2604Bbut does not obfuscate the master ports 2620C and 2620D. The master port2620C is connected to a power source and the master port 2620D is to beconnected to another power source during a test of the integratedcircuit chip design 2608. Also, the master port 2620C is connected to aport of the obfuscated design 2604A shown in FIG. 26B and the masterport 2620D is connected to a port of the obfuscated design 2604B shownin FIG. 26B.

FIG. 28 is a diagram of an embodiment of a system 2800 to illustrate atry before buy option 2802. A user or a requester uses a computingdevice, such as the requester computing device 1 or the user computingdevice 1, to access the try before buy option 2802 via an account, suchas the user account 1 or the requester account 1. The try before buyoption 2802 is generated by the management server 152 for display on thecomputing device. Furthermore, the user or the requester accesses viathe account the workspace application 180 to further access the layoutdesign tool 166. Moreover, upon receiving the selection of the trybefore buy option 2802 and the request for accessing the layout designtool 166, the obfuscator tool 182 sends the obfuscated design 2502 viathe computer network 110 to the computing device for display via theaccount. For the purposes of FIG. 28, a circuit schematic from which theobfuscated design 2502 is generated is created by the user 2 via theuser account 2.

The user, such as the user 1, or the requester uses an input device ofthe computing device to connect, via one or more connections, such as aconnection 2808, the obfuscated design 2502 with a design 2806, such asa layout design, to generate an integrated circuit chip design 2810.Examples of the design 2806 include the design A and the design B ofFIG. 4B-2. To illustrate, the design 2806 is created by the user 1 byaccessing the layout design tool 166. Other examples of the design 2806include the integration circuit logic 452 of FIG. 4B-2. It should benoted that the obfuscated design 2502 does not display the layoutfeatures and associated scaled representations, such as whether atransistor obfuscated within the obfuscated design 2502 is an n-type ora p-type transistor, or a type of a logic gate, or a number of logicgates obfuscated within the obfuscated design 2502, or contacts withcomponents within the obfuscated design 2502, or types of wells usedwithin the obfuscated design 2502, or depths of the wells, or lengths ofthe wells, or widths of the wells, or types of diffusions used withinthe obfuscated design 2502, or depths of the diffusions, or lengths ofthe diffusions, or widths of the diffusions, or a number of oxide layercuts within the obfuscated design 2502, or an arrangement of GDS layerswithin the obfuscated design 2502, or a location of the GDS layers withrespect to each other within the obfuscated design 2502, or locations ofpolysilicons within the layout design 2502, or widths of thepolysilicons, or lengths of the polysilicons, or a number of contactswithin the obfuscated design 2502, or metals that connect one componentto another within the obfuscated design 2502. Examples of types of logicgates include an AND gate, an OR gate, a NOR gate, a NAND gate, abuffer, and a NOT gate. A type of logic gate performs a differentfunction than a different type of logic gate. For example, the NOT gatechanges a bit 1 to a bit 0 and the buffer allows passage of the bit 1 atits input to output a bit 1 at its output. Moreover, the user orrequester verifies functionality of the integrated circuit chip design2810 by accessing the local layout verification tool 167 or the layoutdesign verification tool 190 via the computer network 110 and theaccount.

In an embodiment, the user or requester does not need to pay to try theobfuscated design 2502, such as using the obfuscated design 2502 withthe design 2806. For example, the credit and debit server system doesnot debit a financial account of the user 2 via the computer network 110to credit a financial account of the user 1 to pay the user 2 for use,such as a simulation, of the obfuscated design 2502.

FIG. 29 is a diagram of an embodiment of an integrated circuit chipdesign 2900 that is obfuscated by the obfuscator tool 182. Theintegrated circuit chip design 2900 includes multiple transistors 2904A,2904B, 2904C, and 2904D. Moreover, the integrated circuit chip design2900 includes one or more internal ports, such as an internal port2902A, an internal port 2902B, an internal portion 2902C, and aninternal port 2902D. An example of the internal port 2902D is the port2504A (FIG. 25) and an example of the internal port 2902B is the port2504B (FIG. 25). Moreover, the internal port 2902A is coupled to a powersource and the internal port 2902C is coupled to a ground potential oranother power source. Similarly, each of the remaining transistors 2904Bthrough 2904C is surrounded by internal ports.

Moreover, the integrated circuit chip design 2900 has one or moreexternal ports, such as an external port 2906A and an external port2906B. Each external port is coupled to an external port of anotherintegrated circuit chip design. Moreover, each external port of theintegrated circuit chip design 2900 is coupled to one or more internalports of the integrated circuit chip design 2900.

The user 1 accesses the layout design tool 166 to generate theintegrated circuit chip design 2900. Layout features of the transistors2904A through 2904D are obfuscated by the obfuscator tool 182. Forexample, the obfuscator tool 182 hides a type of any of the transistors2904A through 2904D. The user 1 accesses via the user account 1 and thecomputer network 110 the layout design tool 166 to select widths of thetransistors 2904A through 2904D, lengths of the transistors 2904Athrough 2904D, and a number of the transistors 2904A and 2904D. Thelayout design tool 166 is accessed to position the transistors 2904Athrough 2904D, to connect via the input device of the user computingdevice 1 the internal ports of the integrated circuit chip design 2900,and to connect one or more of the internal ports of the integratedcircuit chip design 2900 with one or more external ports of theintegrated circuit chip design 2900. Also, the user 1 uses the inputdevice of the user computing device 1 to access the layout design tool166 to connect the external ports of the integrated circuit chip design2900 with external ports of another integrated circuit chip design.

In one embodiment, one or more internal ports that surround a transistorof the integrated circuit chip design 2900 is coupled to one or moreinternal ports that surround another transistor of the integratedcircuit chip design 2900. In an embodiment, instead of each transistor2904A through 2904C, another IP cell, such as a logic gate, multipletransistors, multiple logic gates, one or more inductors, one or morecapacitors, one or more resistors, or a combination thereof, is used inthe nitrated circuit chip design 2900. In one embodiment, each internalport, such as any of the internal ports 2902A through 2902D, has one ormore contacts and the contacts are coupled to gates of differenttransistors. In an embodiment, the terms external port and master portare used herein interchangeably.

FIG. 30 is a diagram of an embodiment of a system 3000 for mapping a GDSlayer of a layout design to a plane. The fabrication entity PDK includesmultiple GDS layers, such as the layout features, that can be used bythe user 1 to generate a layout design when there is an NDA between afabrication entity that owns intellectual property rights to thefabrication entity PDK and the user 1. In case of an absence of the NDA,the obfuscator tool 182 of the DES PDK maps one or more GDS layers ofthe fabrication entity PDK to a plane of the DES PDK to obfuscate alayout design that has the GDS layers. For example, the obfuscator tool182 maps, such as establishes a one-to-one correspondence with, orassigns, or creates a unique relationship between, a GDS layer 1 of alayout design to a well plane of the DES PDK. Moreover, in this example,the obfuscator tool 182 maps a GDS layer 2 of the layout design to thewell plane. An illustration of the GDS layer 1 is a well type 1, such asan n-type well, and an illustration of the GDS layer 2 is a well type 2,such as a p-type well or a DNwell or a Pwell. The well type 2 isdifferent from the well type 1.

As another example, the obfuscator tool 182 places GDS layers within alayout design on a plane. To illustrate, the obfuscator tool 182 placeswells of different types of a layout design on the well plane.Continuing with the example, instead of sending the GDS layers via thecomputer network 110 to an account for display on a computing device,such as a user computing device or a requester computing device, theobfuscator tool 182 combines two or more GDS layers into one or moreplanes and sends the planes, instead of the GDS layers, via the computernetwork 110 to the computing device for display via the account.

As another example, the obfuscator tool 182 maps a GDS layer 3 of thelayout design to a plane 1 of the DES PDK. The plane 1 is differentfrom, such as not the same as, the well plane. Moreover, in thisexample, the obfuscator tool 182 maps a GDS layer 4 of the layout designto the plane 1. An illustration of the GDS layer 3 is a via 1 thatconnects two layout features of the layout design through a layer, suchas a dielectric layer, of the layout design and an illustration of theGDS layer 3 is a metal layer 1 that connects two layout features of thelayout design.

As yet another example, the obfuscator tool 182 maps a GDS layer 5 ofthe layout design to a plane 2 of the DES PDK. The plane 2 is differentfrom, such as not the same as, the well plane and is different from theplane 1. Moreover, in this example, the obfuscator tool 182 maps a GDSlayer 6 of the layout design to the plane 2. An illustration of the GDSlayer 5 is a via 2 that connects two layout features of the layoutdesign through a layer, such as a dielectric layer, of the layout designand an illustration of the GDS layer 6 is a metal layer 2 that connectstwo layout features of the layout design. In one embodiment, the metallayer 2 is located above the metal layer 1 in the layout design.

As another example, the obfuscator tool 182 maps a GDS layer 7 of thelayout design to an active plane of the DES PDK. The active plane isdifferent from, such as not the same as, the well plane, is differentfrom the plane 1, and is different from the plane 2. Moreover, in thisexample, the obfuscator tool 182 maps a GDS layer 8 of the layout designto the active plane. An illustration of the GDS layer 7 is an oxide cutthat is laid over a layout feature of the layout design to protect thelayout feature and an illustration of the GDS layer 8 is a diffusion oftype 1, such as n-type or p-type diffusion, within a layout feature ofthe layout design.

Continuing with the example, the obfuscator tool 182 maps a GDS layer 9of the layout design to the active plane of the DES PDK. Moreover, inthis example, the obfuscator tool 182 maps a GDS layer 10 of the layoutdesign to the active plane. An illustration of the GDS layer 9 is adiffusion of type 2, such as n-type or p-type diffusion, within a layoutfeature of the layout design, and an illustration of the GDS layer 10 isa contact 1 of the layout design. The contact 1 is coupled to a layoutfeature of the layout design. The diffusion of the type 2 is differentfrom the diffusion of the type 1. To illustrate, the type 2 diffusion isp-type and the type 1 diffusion is n-type.

Continuing further with the example, the obfuscator tool 182 maps a GDSlayer 11 of the layout design to the active plane of the DES PDK.Moreover, in this example, the obfuscator tool 182 maps a GDS layer 12of the layout design to the active plane. An illustration of the GDSlayer 11 is a contact 2 of the layout design and an illustration of theGDS layer 12 is a polysilicon 1 of the layout design. The contact 2 iscoupled to a different layout feature of the layout design than a layoutfeature to which the contact 1 is coupled. As an illustration, apolysilicon is used as a gate electrode.

Continuing with the example, the obfuscator tool 182 maps a GDS layer 13of the layout design to the active plane of the DES PDK. Moreover, inthis example, the obfuscator tool 182 maps a GDS layer 14 of the layoutdesign to the active plane. An illustration of the GDS layer 13 is apolysilicon 2 of the layout design and an illustration of the GDS layer14 is an active device or a passive device of the layout design. Thepolysilicon 2 is different from the polysilicon 1. To illustrate, thepolysilicon 2 is a material used to fabricate a different gate electrodethan a gate electrode fabricated from polysilicon 1. Examples of theactive device include a varactor diode, a transistor, an NMOS, a PMOS, arectifier, and a logic gate. Examples of the passive device include aresistor, a capacitor, and an inductor.

The obfuscator tool 182 maps a GDS layer 15 of the layout design to animplant plane of the DES PDK. The implant plane is different from, suchas not the same as, the well plane, is different from the plane 1, isdifferent from the plane 2, and is different from the active plane.Moreover, in this example, the obfuscator tool 182 maps a GDS layer 16of the layout design to the implant plane. An illustration of the GDSlayer 15 is an ion implant type 1 of the layout design and anillustration of the GDS layer 16 is an ion implant type 2 of the layoutdesign. The ion implant type 2 is different from the ion implant type 1.To illustrate, the ion implant type 1 is an n-type implant and the ionimplant type 2 is a p-type implant.

When the user N requests via the user account N for the layout design,the obfuscator tool 182 obfuscates two or more of the GDS layers 1through 16 of the layout design and sends the well plane, the plane 1,the plane 2, and/or the implant plane via the computer network 110 tothe user computing device N for display via the user account N. Forexample, the obfuscator tool 182 determines that the user account N doesnot have permission to view the GDS layers 1 through 16 and upondetermining so, the obfuscator tool 182 maps the GDS layers 1 and 2 tothe well plane, the GDS layers 3 through 6 to the plane 1, the GDSlayers 7 through 14 to the plane 2, and/or the GDS layers 15 and 16 tothe implant plane, and sends the well plane, the plane 1, the plane 2,and/or the implant plane to the user computing device 1 for display onthe display device of the user computing device 1. To illustrate,instead of sending any two GDS layers via the computer network to theuser computing device 1 for display via the user account 1, theobfuscator tool 182 generates a plane from the GDS layers and sends theplane via the computer network 110 to the user computing device 1 fordisplay via the user account 1.

In an embodiment, a GDS layer on a plane cannot overlap with a GDS layerof a different type. For example, the well type 1 cannot overlap withthe well type 2. As another example, the diffusion type 1 cannot overlapwith the diffusion type 2. As yet another example, the implant type 1cannot overlap with the implant type 2.

In an embodiment, the obfuscator tool 182 establishes a mapping betweena GDS layer of the fabrication entity PDK and a plane of the DES PDK bygenerating a pointer from a memory address of the searchable storage 162in which data of the GDS layer is stored to a memory address of thesearchable storage 162 in which data of the plane is stored. In anotherembodiment, the obfuscator tool 182 establishes a mapping between a GDSlayer of the fabrication entity PDK and a plane of the DES PDK bygenerating a pointer from a memory address of the searchable storage 162in which data of the plane is stored to a memory address of thesearchable storage 162 in which data of the GDS layer is stored.

FIG. 31 is a diagram of an embodiment of a system 3100 to illustrategeneration of a derived type from two or more GDS layers. An example ofa derived type is a layout feature. The obfuscator tool 182 combines aGDS layer A and a GDS layer B of a layout design to generate a derivedtype 3102, which is a layout feature of the derived type. For example,when the user N operates the user computing device N to access thelayout design tool 166 to further access a layout design from the designdatabase 160, the obfuscator tool 182 accesses the public-privateindicator database 220 to determine whether the user account N haspermission to access the layout design. Upon determining that the useraccount N does not have the permission, the obfuscator tool 182integrates the GDS layers A and B of the layout design to generate thederived type 3102 to obfuscate the GDS layers A and B. The obfuscatortool 182 sends the derived type 3102, instead of the GDS layers A and B,via the computer network 110 to the user computing N for display via theuser account N. On the other hand, upon determining that the useraccount N has the permission, the obfuscator tool 182 does not integratethe GDS layers A and B of the layout design to generate the derived type3102, and sends the GDS layers A and B via the computer network 110 tothe user computing N for display via the user account N. Examples of theGDS layer A include any of the GDS layers 1 through 16 and examples ofthe GDS layer B includes any remaining layers of the GDS layers 1through 16 that are not the GDS layer A. Additional examples of the GDSlayer A include any of layout features of the layout design and of theGDS layer B include any of remaining features of the layout design. Noneof the remaining features is the GDS layer A. The derived type 3102 isgenerated to obfuscate two or more of the GDS layers 1 through 16.

As an example, an implant type, such as n-type or p-type implant, of thelayout design is merged by the obfuscator tool 182 with an active device1 of the layout design to generate an ndiff derived type. Illustrationsof the active device 1 include any of the active devices, such as atransistor and a logic gate, described above. As another example, animplant type of the layout design is merged by the obfuscator tool 182with the active device 1, a contact 1 of the layout design, and a metal1 of the layout design to generate an ndiffcont derived type. Anillustration of the contact 1 is a metal contact to a gate or a sourceor a drain of a transistor. Another illustration of the contact 1 is ametal contact to an input of a logic gate or an output of the logicgate. Yet another illustration of the contact 1 is a metal contact to aterminal of a resistor or a capacitor or an inductor. An illustration ofthe metal 1 is a metal connection between two layout features of thelayout design. As yet another example, an implant type of the layoutdesign is merged by the obfuscator tool 182 with the active device 1,one or more contacts of the layout design, and the metal 1 of the layoutdesign to generate the ndiffcont derived type. As another example, theactive device 1 of the layout design is merged by the obfuscator tool182 with an implant type of the layout design, a polysilicon 1 of thelayout design, and an oxide cut of the layout design to generate an nmosderived type. An illustration of the polysilicon 1 is a polysiliconlayer of an electrode of a transistor. An illustration of the oxide cutis an oxide layer that is deposited on a layout feature to protect thelayout feature. As yet another example, a via 1 of the layout design iscombined by the obfuscator tool 182 with the metal 1, a metal 2 of thelayout design to generate a vial derived type. As an illustration, themetal 2 connects two layout features of the layout design and at leastone of the layout features connected via the metal 2 is different thanat least one of the layout features connected via the metal 1. Anillustration of the via 1 is a via between two layout features of thelayout design. The via extends through a layer, such as an oxide layeror a dielectric layer, or both the layers, of the layout design. Asanother example, the polysilicon 1 is merged by the obfuscator tool 182with a polysilicon 2 of the layout design to generate a polycap derivedtype. As an illustration, the polysilicon 2 is polysilicon of adifferent terminal of a transistor compared to the polysilicon 1. Tofurther illustrate, the polysilicon 2 is polysilicon of a gate of atransistor and the polysilicon 1 is polysilicon is of a drain of thetransistor. As another illustration, the polysilicon 2 is polysilicon ofa terminal of a different transistor compared to the polysilicon 1. Tofurther illustrate, the polysilicon 2 is polysilicon of a gate of atransistor and the polysilicon 1 is polysilicon is of a gate of anothertransistor.

In one embodiment, the obfuscator tool 182 combines two or more GDSlayers to generate a derived type after the GDS layers are placed on aplane. For example, the GDS layers A and B are mapped to a plane. Afterthe mapping, the obfuscator tool 182 combines the GDS layers A and Binto a derived type, which is located on the plane. As another example,more than two GDS layers are mapped to a plane. After the mapping, theobfuscator tool 182 combines the more than two GDS layers into a derivedtype, which is located on the plane.

FIG. 32 is a diagram of an embodiment of a listing of obfuscator rulesthat are applied by the obfuscator tool 182 to obfuscate one or morelayout features of a layout design. When the user N operates the usercomputing device N to access the layout design tool 166 via the useraccount N to generate the layout design, the obfuscator tool 182 appliesone or more of the obfuscator rules to determine whether to permit theuser N via the input device of the user computing device N to generateor modify a layout feature of the layout design. For example, theobfuscator tool 182 permits the user N via the user account N to selectspacing between two wells of the layout design but does not allow theuser N to select via the user account N widths of the wells and does notallow the user N to draw via the user account N the wells. As anotherexample, the obfuscator tool 182 prevents the user N via the useraccount N to select the spacing between the two wells, the widths of thewells, and/or to draw the wells. As another example, the obfuscator tool182 allows the user N via the user account N to draw a diffusion type 1of the layout design, to select a width of the diffusion type 1, and toselect spacing between two diffusion types of the layout design. As anexample, the obfuscator tool 182 prohibits the user N via the useraccount N to draw the diffusion type 1 of the layout design, to selectthe width of the diffusion type 1, and/or to select the spacing betweentwo diffusion types 1 of the layout design. As another example, theobfuscator tool 182 does not allow the user N via the user account N todraw a diffusion type 2 of the layout design and to select a width ofthe diffusion type 2, and allows the user N via the user account N toselect spacing between two diffusion types of the layout design. As anexample, the obfuscator tool 182 prevents the user N via the useraccount N to draw the diffusion type 2 of the layout design, to selectthe width of the diffusion type 2, and/or to select the spacing betweentwo diffusion types 2 of the layout design. The diffusion type 2 isdifferent from the diffusion type 1. To illustrate, the diffusion type 1is an n-type diffusion within a well and the diffusion type 2 is ap-type diffusion within another well.

As another example, the obfuscator tool 182 does not permit the user Nvia the user account N to draw a polysilicon of the layout design, toselect a width of the polysilicon, and to select a spacing between twopolysilicons of the layout design. As another example, the obfuscatortool 182 prevents the user N via the user account N to draw thepolysilicon of the layout design, to select the width of thepolysilicon, and/or to select the spacing between two polysilicons ofthe layout design. As an example, the obfuscator tool 182 permits theuser N via the user account N to draw a metal, such as a metalconnection between two layout features, of the layout design, to selecta width of the metal, and to select a spacing between two metals of thelayout design. As another example, the obfuscator tool 182 prohibits theuser N via the user account N to draw the metal of the layout design, toselect the width of the metal, and/or to select the spacing between twometals of the layout design.

As an example, the obfuscator tool 182 permits the user N via the useraccount N to draw a via, such as a via connecting two layout features,of the layout design, to select a width of the via, and to select aspacing between two vias of the layout design. As another example, theobfuscator tool 182 prevents the user N via the user account N to draw avia of the layout design, to select a width of the via, and/or to selecta spacing between two vias of the layout design. As an example, theobfuscator tool 182 does not permit the user N via the user account N todraw an active device of the layout design, to select a width of theactive device, and to select a spacing between two active devices of thelayout design. As another example, the obfuscator tool 182 prevents theuser N via the user account N to draw an active device of the layoutdesign, to select a width of the active device, and/or to select aspacing between two active devices of the layout design.

FIG. 33 is a diagram of an embodiment of an integrated circuit chipdesign 3300, which is obfuscated by the obfuscator tool 182 bygenerating derived types. The integrated circuit chip design 3300includes four ndiffcont derived types 3302A, 3302B, 3302C, and 3302D.Moreover, the integrated circuit chip design 3300 further includes threenmos derived types 3304A, 3304B, and 3304C. Each nmos derived type3304A, 3304B, and 3304C is located between two ndiffcont derived types.The integrated circuit chip design 3300 includes three ndiff derivedtypes 3306A, 3306B, and 3306C. Each ndiff derived type 3306A, 3306B, and3306C is adjacent to two ndiffcont derived types.

Moreover, the nmos derived type 3304A is coupled to a polysilicon 3312A,such as the polysilicon 1, at one end and to a polysilicon 3312F at anopposite end. Similarly, the nmos derived type 3304B is coupled to apolysilicon 3312B at one end and to a polysilicon 3312E at an oppositeend. Also, the nmos derived type 3304C is coupled to a polysilicon 3312Cat one end and to a polysilicon 3312D at an opposite end.

The polysilicon 3312A is coupled to a contact 3308A of the integratedcircuit chip layout design 3300 and the polysilicon 3312B is coupled toa contact 3308B of the integrated circuit chip layout design 3300.Moreover, the polysilicon 3312C is coupled to a contact 3308C of theintegrated circuit chip layout design 3300 and the polysilicon 3312D iscoupled to a contact 3308F of the integrated circuit chip layout design3300. Also, the polysilicon 3312E is coupled to a contact 3308E of theintegrated circuit chip layout design 3300 and the polysilicon 3312F iscoupled to a contact 3308D of the integrated circuit chip layout design3300.

Moreover, the integrated circuit chip layout design 3300 includes acontact 3310A and another contact 3310B. Each of the contacts 3310A and3310B is an example of a port to couple a diffusion 3313 within a p-typesubstrate of the integrated circuit chip design 3300 to anotherintegrated circuit chip design to test the integrated circuit chipdesign 3300 or the other integrated circuit chip design.

FIG. 34 is a diagram of an embodiment of an integrated circuit chipdesign 3400 to illustrate multiple derived types. The integrated circuitchip design 3400 has an arrangement of a derived type rnp1, which isgenerated by the obfuscator tool 182 by combining two or more GDS layersdescribed above. For example, four blocks 3402A, 3402B, 3402C, and 3402Dare arranged in a row. Each block 3402A, 3402B, 3402C, and 3402D is ofthe derived type rnp1. Each block 3402A, 3402B, 3402C, and 3402D of thederived type rnp1 is coupled to a contact at both ends. As an example,the block 3402A is connected to a contact 3404A at one end of the block3402A and to a contact 3404B at its opposite end of the block 3402A. Asanother example, the block 3402B is coupled to a contact 3404C at oneend of the block 3402B and to a contact 3404D at an opposite end of theblock 3402B. Similarly, the block 3402C is coupled to a contact at oneend of the block 3402C and to another contact at another end of theblock 3402C. Moreover, the block 3402D is coupled to a contact at oneend of the block 3402D and to another contact at another end of theblock 3402D. Furthermore, the integrated circuit chip design 3400includes an n-type well 3406, multiple contacts 3408A and 3408B to an-type substrate of the integrated circuit chip design 3400, and adiffusion 3410 within the n-type substrate.

In one embodiment, each contact of the integrated circuit chip design3400 that is coupled to a block, such as the block 3402A, 3402B, 3402C,and 3402D, is a combination, generated by the obfuscator tool 182, ofcontacts. For example, the contact 3404A is a combination of two or morecontacts. One of the two or more contacts is connected to a GDS layer ofa layout design and another one of the two or more contacts is connectedto another GDS layer of the layout design. For example, one of the twomore contacts is connected to a gate of a transistor of the layoutdesign in another one of the two or more contacts is connected to adrain of the same or a different transistor of the layout design.

FIG. 35 is a diagram to illustrate an embodiment of an obfuscatedintegrated circuit chip design 3502 that is generated from an integratedcircuit chip design 3504. The obfuscated tool 182 accesses theintegrated circuit chip design 3504 from the design database 160 of FIG.1B-2 and obfuscates one or more layout features of the integratedcircuit chip design 3504 to generate the obfuscated integrated circuitchip design 3502. The layout features of the integrated circuit chipdesign 3504 include NMOS transistors 3506, PMOS transistors 3508, mergedcontacts 3510, and a resistor 3512. In one embodiment, the mergedcontacts 3510 are referred to herein as a combined contact that has acombination of two or more contacts. The two or more contacts arecombined by the obfuscator tool 182. It should be noted that in theobfuscated integrated circuit chip design 3502, the NMOS transistors3506, the PMOS transistors 3508, the merged contacts 3510, and theresistor 3512 are not visible, such as, are opaque or are hidden. Forexample, when the user N operates the user computing device N to accessvia the layout design tool 166 the integrated circuit chip design 3504from the design database 160, the obfuscated tool 182 renders as opaquethe NMOS transistors 3506, the PMOS transistors 3508, the mergedcontacts 3510, and the resistor 3512 to generate the obfuscatedintegrated circuit chip design 3502. The obfuscated tool 182 sends theobfuscated integrated circuit chip design 3502 via the computer network110 to the user computing device N for display by the user account N onthe display device of the user computing device N.

FIG. 36A is an embodiment of an unobfuscated layout design 3600 of aninverter. The layout design 3600 has a p-type substrate 3602. An n-typewell 3604 is formed within the p-type substrate 3602. Moreover, a dopantis added within the n-type well 3604 to form a p-type diffusion 3606Aand is also added at a different position within the n-type well 3604 toform another p-type diffusion 3606B. Also, a dopant is added within then-type well 3604 to form an n-type diffusion 3608 within the n-well3604.

Similarly, a dopant is added within the p-type substrate 3602 to form ann-type diffusion 3610A and is also added at a different position withinthe p-type substrate 3602 to form another n-type diffusion 3610B. Also,a dopant is added within the p-type substrate 3602 to form a p-typediffusion 3612 within the p-type substrate 3602.

Moreover, an oxide layer cut OCT1 is formed on top of the p-typesubstrate 3602 and a portion of the p-type diffusion 3612. In addition,an oxide layer cut OCT2 is formed on top of a portion of the p-typediffusion 3612 and a portion of the n-type diffusion 3610A. Also, anoxide layer cut OCT3 is formed on top of a portion of the n-typediffusion 3610A, a portion of the p-type substrate 3602, and a portionof the n-type diffusion 3610B. An oxide layer cut OCT4 is formed on topof a portion of the n-type diffusion 3610B, a portion of the p-typesubstrate 3602, a portion of the n-type well 3604, and a portion of thep-type diffusion 3606A. Moreover, an oxide layer cut OCT5 is formed ontop of a portion of the p-type diffusion 3606A, a portion of the n-typewell 3604, and a portion of the p-type diffusion 3606B. Also, an oxidelayer cut OCT6 is formed on top of a portion of the p-type diffusion3606B and a portion of the n-type diffusion 3608. Also, an oxide layercut OCT7 is formed on top of a portion of the n-type diffusion 3608, aportion of the n-type well 3604, and a portion of the p-type substrate3602. An oxide cut is made from silicon dioxide.

A metal layer portion 1 is fabricated on top of the oxide layer cuts 1and 2, and on top of the p-type diffusion 3612 and the n-type diffusion3610A, and is adjacent to the oxide layer cut OCT3. Moreover, a metallayer portion 2 is fabricated on top of the n-type diffusion 3610B, theoxide layer cut 4, the p-type diffusion 3606A, and is adjacent to theoxide layer cuts OCT3 and OCT 5. A metal layer portion 3 is fabricatedon top of the p-type diffusion 3606B, the n-type diffusion 3608, and ontop of the oxide layer cuts 6 and 7, and is adjacent to the oxide layercut OCT5. The metal layer portion 1 is a ground connection, for example,is at a ground potential. Moreover, the metal layer portion 2 is anoutput, such as an output port, of the unobfuscated layout design 3600and the metal layer portion 3 is at a potential VDD, which is differentfrom the ground potential. The oxide layer cut OCT3 surrounds apolysilicon PS1, which represents a gate electrode, and the oxide layercut OCT5 surrounds a polysilicon PS2, which represents another gateelectrode. Both the polysilicons PS1 and PS2 are coupled to each otherto form an input, such as an input port, of the unobfuscated layoutdesign 3600.

The n-type diffusion 3610A, the polysilicon PS1, and the n-typediffusion 3610B together form an active device, such as an NMOStransistor. Moreover, the p-type diffusion 3606A, the polysilicon PS2,and the n-type diffusion 3606B form another active device, such as aPMOS transistor.

In one embodiment, a metal layer portion of a layout design is sometimesreferred to herein as a metal of the layout design.

FIG. 36B is a diagram of an embodiment of a top view 3620 of the layoutdesign 3600 of FIG. 36A. The top view 3620 shows multiple contacts CT1,CT2, CT3, CT4, CT5, and CT6 of the layout design. The contact CT1connects to the p-type diffusion 3612 and the contact CT2 connects tothe n-type diffusion 3610A. Moreover, the contact CT3 connects to then-type diffusion 3610B. The contact CT4 connects to the p-type diffusion3636A. The contact CT5 connects to the p-type diffusion 3606B and thecontact CT6 connects to the n-type diffusion 3608.

It should be noted that each layout feature of the layout design 3600has a size, such as a width, a length, and a depth. For example, then-type well 3604 has a depth d1, a width w1, and a length l1. As anotherexample, the metal layer portion 1 has a depth d2, a width w2, and alength l2.

A1. A system for obfuscating a circuit design, comprising:

a circuit design tool configured to receive the circuit design from auser computing device via a computer network and a user account, whereinthe circuit design includes a plurality of circuit components andconnections between the circuit components, wherein one of the circuitcomponents is of a different type than one of remaining of the circuitcomponents, wherein each circuit component has an input and an output;

an obfuscator tool coupled to the circuit design tool, wherein theobfuscator tool is configured to obfuscate the types of the circuitcomponents to generate an obfuscated design for each component; and

a layout design tool coupled to the obfuscator tool, wherein the layoutdesign tool is configured to receive, from the user computing device viathe user account and the computer network, a request for accessing thelayout design tool,

wherein the obfuscator tool is configured to send the obfuscated designof each of the circuit components to the user computing device via theuser account and the computer network when the request to access thelayout design tool is received

A2. The system of claim A1, wherein the obfuscator tool is configured tocombine a first Graphics Database System (GDS) layer with a second GDSlayer to generate a derived type.

A3. The system of claim A2,

wherein the first GDS layer is a type of ion implant, the second GDSlayer is an active device, and the derived type is a type of diffusion,or

wherein the first GDS layer is a first polysilicon and the second GDSlayer is a second polysilicon.

A4. A non-transitory computer readable medium containing programinstructions for obfuscating a circuit design, wherein execution of theprogram instructions by one or more processors of a computer systemcauses the one or more processors to carry out a plurality of operationsof:

receiving the circuit design from a user computing device via a computernetwork and a user account, wherein the circuit design includes aplurality of circuit components and connections between the circuitcomponents, wherein one of the circuit components is of a different typethan one of remaining of the circuit components, wherein each circuitcomponents has an input and an output;

obfuscating, by an obfuscator tool, the circuit components to obfuscatethe types of the circuit components to generate an obfuscated design foreach component;

receiving, from the user computing device by the user account and thecomputer network, a request to access a layout design tool; and

sending the obfuscated design of each of the circuit components to theuser computing device via the user account and the computer network uponreceiving the request to access the layout design tool.

A5. The non-transitory computer readable medium of claim A4, furthercomprising allowing, by the layout design tool, the user account toplace the obfuscated designs of the circuit components and to generaterouting between the obfuscated designs to generate an integrated circuitchip design.

A6. The non-transitory computer readable medium of claim A5, furthercomprising:

receiving a request to access the integrated circuit chip design viaanother user account and the computer network;

obfuscating, by the obfuscator tool, the integrated circuit chip designto generate an obfuscated integrated circuit design; and

sending the obfuscated integrated circuit design by the computer networkto the other account.

A7. The non-transitory computer readable medium of claim A6, wherein theobfuscated integrated circuit design is an opaque design object thatcovers the types of the circuit components, the placement of the circuitcomponents, and the routing between the circuit components.

A8. A non-transitory computer readable medium containing programinstructions for obfuscating a circuit design, wherein execution of theprogram instructions by one or more processors of a computer systemcauses the one or more processors to carry out a plurality of operationsof:

receiving the circuit design from a user computing device via a computernetwork and a user account, wherein the circuit design includes aplurality of circuit components and connections between the circuitcomponents;

obfuscating each of the circuit components by transforming layoutfeatures associated with the circuit design into a generic layoutfeature representation, wherein the generic layout featurerepresentation excludes scaled representations of the layout features,wherein said obfuscating is performed so that each circuit component isrepresented as an obfuscated design that has electrical characteristicsof the circuit component and excludes access to the layout features ofthe circuit component;

generating a visual representation of the obfuscated designs, whereineach of the obfuscated designs has an input port and an output port;

enabling placement of the obfuscated designs and routing between theinput ports and the output ports of the obfuscated designs; and

generating an obfuscated integrated circuit design having a master inputport, a master output port, the obfuscated designs, and the routingbetween the obfuscated designs, wherein the obfuscated integratedcircuit design is accessible to simulate the circuit design withoutexposing the circuit design such that the simulation of the circuitdesign is performed while the circuit components are obfuscated.

A9. The non-transitory computer readable medium of claim A8, wherein theobfuscated integrated circuit design is an opaque object that obfuscatesthe circuit components and the routing between the obfuscated designs,and does not hide the master input port and the master output port.

A10. The non-transitory computer readable medium of claim A8, whereinthe generic layout feature representation obfuscates a number of thelayout features, wherein the scaled representations include widths,lengths, and depths of the layout features.

It should be noted that some of the above-described embodiments aredescribed with respect to functions executed by a server, such as themanagement server 152. In various embodiments, the functions describedherein as being performed by one server are performed by multipleservers, such as two or more servers. For example, one of the multipleservers performs some of the functions and another one of the serversperformed remaining of the functions.

It should be noted that some of the above-described embodiments aredescribed with respect to functions executed by a processor, such as aprocessor of the management server 152. In various embodiments, thefunctions described herein as being performed by one processor of aserver are performed by multiple processors, such as two or moreprocessors, of the server or of different servers. For example, one ofthe multiple processors performs some of the functions and another oneof the processors performed remaining of the functions.

In one aspect, one or more embodiments described in the presentdisclosure are fabricated as computer-readable code on acomputer-readable storage medium, which is a storage device or a memorydevice. The computer-readable storage medium holds data which isreadable by a processor. Examples of the computer-readable storagemedium include network attached storage (NAS), a memory device, a ROM, aRAM, a combination of RAM and ROM, a Compact Disc (CD), a Blu-ray™ disc,a flash memory, a hard disk, and a magnetic tape. The computer-readablestorage medium, in one embodiment, is distributed over a network-coupledcomputer system so that the computer readable code is stored andexecuted in a distributed fashion.

In one embodiment, some features described in one of the embodimentsdescribed above are combined with some features described in another oneof the embodiments described above.

Although the embodiments described in the present disclosure have beendescribed in detail for purposes of clarity of understanding, it will beapparent that certain changes and modifications can be practiced withinthe scope of the appended claims. Accordingly, the embodiments are to beconsidered as illustrative and not restrictive, and the embodiments arenot to be limited to the details given herein, but may be modifiedwithin the scope and equivalents of the appended claims.

1. A method for obfuscating a layout design for a system-on-a-chip(SoC), comprising: receiving, by a server, the layout design for theSoC; determining that a request to access the layout design is receivedvia a user account that does not have permission to view the layoutdesign; obfuscating, by the server, the layout design to produce anobfuscated design upon determining that the user account does not havepermission to view the layout design, wherein the obfuscated designexcludes scaled representations of layout features of the layout design,wherein said obfuscating is performed to maintain electricalcharacteristics of a plurality of components of a circuit associatedwith the layout design and excludes access to the layout featuresassociated with the plurality of components; and providing access to theobfuscated design via the user account in response to the request,wherein the access to the obfuscated design is provided to facilitatetesting of functionality of the circuit without exposing the layoutfeatures and interconnections of the plurality of components.
 2. Themethod of claim 1, wherein said determining that the request is receivedvia the user account that does not have the permission is performed uponaccessing a database that includes a plurality of associations between aplurality of user accounts and a plurality of permissions indicatingwhether the plurality of user accounts are permitted access to thelayout design.
 3. The method of claim 1, wherein the user account isassigned to a user, wherein an indication that the user account is notto be permitted access to the layout design is received via a computernetwork and another user account that is assigned to another user. 4.The method of claim 3, wherein the user account and the other useraccount are assigned to create members of an online community that ismanaged by one or more servers.
 5. The method of claim 1, wherein saidobfuscating includes overlaying the layout features with an opaqueportion to hide the layout features of the layout design from beingshown via the user account.
 6. The method of claim 1, wherein the accessto the obfuscated design is enabled via a computer network and the useraccount to a computing device.
 7. The method of claim 1, wherein thelayout design is received via a computer network and another useraccount from a computing device.
 8. The method of claim 1, wherein thescaled representations of the layout features include widths of thelayout features, lengths of the layout features, and depths of thelayout features, wherein the layout features include an arrangement ofGraphics Database System (GDS) layers of the layout design.
 9. Themethod of claim 1, wherein the electrical characteristics includetransfer characteristics of the plurality of components of the circuit.10. The method of claim 1, wherein the testing of functionality includesdetermining a voltage at an output of the obfuscated design when avoltage is applied at an input of the obfuscated design, wherein duringthe testing, the layout features are covered by an opaque portion fornot exposing the layout features.
 11. The method of claim 1, wherein thetesting of the layout design characterizes functional electricalperformance of the plurality of components without exposing the layoutfeatures, wherein the functional electrical performance includes arelationship between a voltage at an output pin of the obfuscated designand a voltage at an input pin of the obfuscated design.
 12. The methodof claim 1, wherein the layout features are associated with theplurality of components when the layout features are created from acircuit design of the components.
 13. A system for obfuscating a layoutdesign for a system-on-a-chip (SoC), comprising: one or more serversconfigured to: receive the layout design for the SoC; determine that arequest to access the layout design is received via a user account thatdoes not have permission to view the layout design; obfuscate the layoutdesign to produce an obfuscated design upon determining that the useraccount does not have permission to view the layout design, wherein theobfuscated design excludes scaled representations of layout features ofthe layout design, wherein the one or more servers are configured toobfuscate the layout design to maintain electrical characteristics of aplurality of components of a circuit associated with the layout design,wherein the one or more servers are configured to exclude access to thelayout features associated with the plurality of components; and provideaccess to the obfuscated design via the user account in response to therequest, wherein the obfuscated design is provided access to facilitatetesting of functionality of the circuit without exposing the layoutfeatures and interconnections of the plurality of components; and amemory device coupled to the one or more servers.
 14. The system ofclaim 13, wherein the memory device is configured to store a databasethat includes a plurality of associations between a plurality of useraccounts and a plurality of permissions indicating whether the pluralityof user accounts are permitted access to the layout design, wherein theone or more servers are configured to access the plurality ofassociations from the database to determine that the user account is notto be provided access to the layout design.
 15. The system of claim 13,wherein the one or more servers are configured to receive an indicationvia a computer network and another user account that the user account isnot to be permitted access to the layout design, wherein the useraccount is assigned to a user and the other user account is assigned toanother user.
 16. A system for generating an obfuscated design,comprising: one or more processors configured to: receive a processdesign kit from a computing device via a computer network and afabrication entity account; modify the process design kit to integratean obfuscator tool into the process design kit to provide a modifiedprocess design kit; receive a request for accessing a layout design fora system-on-a-chip (SoC) via a user account and the modified processdesign kit; execute the obfuscator tool to obfuscate the layout designto output the obfuscated design; provide the obfuscated design via theuser account and the computer network to another computing device,wherein the obfuscated design is provided with at least one input and atleast one output to enable testing of functionality of the layout designwithout revealing portions of the layout design; and a memory devicecoupled to the one or more processors.
 17. The system of claim 16,wherein the one or more processors are configured to determine whetherthe user account is to be provided access to the layout design, whereinthe obfuscator tool is executed to obfuscate the layout design upondetermining that the user account is not to be allowed access to thelayout design,
 18. The system of claim 17, wherein the memory device isconfigured to store a database that includes a plurality of associationsbetween a plurality of user accounts and a plurality of permissionsindicating whether the plurality of user accounts are permitted accessto the layout design, wherein the one or more processors are configuredto access the plurality of associations from the database to determinethat the user account is not to be provided access to the layout design.19. The system of claim 17, wherein the one or more processors areconfigured to: determine that another request to access the layoutdesign is received via another user account that has permission to viewthe layout design; and enable access to the layout design via the otheruser account in response to the other request.
 20. The system of claim16, wherein the one or more processors are configured to assign the useraccount to a user and another user account to another user to createmembers of an online community.
 21. The system of claim 16, wherein toobfuscate the layout design, the one or more processors are configuredto overlay the portions of the design with an opaque portion to hidelayout features of the layout design from being shown via the useraccount.
 22. The system of claim 16, wherein the process design kitincludes a set of files used to model a fabrication process for a layoutdesign tool, wherein the layout design tool is used to generate thelayout design for the SoC.
 23. The system of claim 16, wherein thefabrication entity account is assigned to a fabrication entity thatmanufactures the SoC.